Squire: A General-Purpose Accelerator to Exploit Fine-Grain Parallelism on Dependency-Bound Kernels

TL;DR

Squire introduces a general-purpose accelerator architecture that exploits fine-grain parallelism in dependency-bound kernels by equipping each host core with a cluster of simple in-order workers and a hardware synchronization module. The design enables low-latency offload, shared memory access, and nested parallelism across data sorting, genomics, and signal-processing kernels, achieving up to 7.64$\times$ speedups on DP kernels and 3.66$\times$ end-to-end with energy reductions up to 56%. Through detailed kernel mappings (Radix Sort, Chain, DTW) and an end-to-end read-mapping tool, the authors demonstrate broad applicability, scalable performance with 8–16 workers, and modest area overhead (~10.5% per core). The work suggests Squire as a viable path to accelerate dependency-bound workloads within mainstream multicore systems, offering substantial practical impact for HPC and data-intensive domains.

Abstract

Multiple HPC applications are often bottlenecked by compute-intensive kernels implementing complex dependency patterns (data-dependency bound). Traditional general-purpose accelerators struggle to effectively exploit fine-grain parallelism due to limitations in implementing convoluted data-dependency patterns (like SIMD) and overheads due to synchronization and data transfers (like GPGPUs). In contrast, custom FPGA and ASIC designs offer improved performance and energy efficiency at a high cost in hardware design and programming complexity and often lack the flexibility to process different workloads. We propose Squire, a general-purpose accelerator designed to exploit fine-grain parallelism effectively on dependency-bound kernels. Each Squire accelerator has a set of general-purpose low-power in-order cores that can rapidly communicate among themselves and directly access data from the L2 cache. Our proposal integrates one Squire accelerator per core in a typical multicore system, allowing the acceleration of dependency-bound kernels within parallel tasks with minimal software changes. As a case study, we evaluate Squire's effectiveness by accelerating five kernels that implement complex dependency patterns. We use three of these kernels to build an end-to-end read-mapping tool that will be used to evaluate Squire. Squire obtains speedups up to 7.64$\times$ in dynamic programming kernels. Overall, Squire provides an acceleration for an end-to-end application of 3.66$\times$. In addition, Squire reduces energy consumption by up to 56% with a minimal area overhead of 10.5% compared to a Neoverse-N1 baseline.

Figures (10)

• Figure 1: Examples of coarse-grain tasks with fine-grain parallelism: (a) sorting, (b) dynamic programming matrix, (c) sparse matrix-vector multiplication. Each color in the data structures represents a chunk of fine-grain work.
• Figure 2: Chain algorithm dependencies. To calculate the score of anchor 4 ($f(4)$), we add all the previous scores to row 4 and perform a maximum. In the next iteration, $f(4)$ will be added to row 5.
• Figure 3: DTW matrix representation. The samples from signal 1 are set at the top of the matrix, while samples from signal 2 are set at the left. For each cell DTW computes Equation \ref{['eq:dtw']}. Arrows indicates the minimum value from Equation \ref{['eq:dtw']}.
• Figure 4: Squire architectural overview: (a) the simulated multi-core system with a 4x4 NoC and four memory controllers, where each central router holds a core complex and one slice of the L3 cache; (b) a core complex contains one OoO core with private L1 caches, a private L2 cache, and a Squire; (c) Squire contains a set of workers, several control registers, a synchronization module, and an arbiter to communicate with the memory hierarchy (L2).
• Figure 5: DTW work distribution among workers. Worker 0 (W0) computes columns 0 and 1, worker 1 (W1) columns 2 and 3, worker 2 (W2) columns 4 and 5, and worker 3 (W3) columns 6 and 7. The workers compute the cells following the path indicated by the arrows.