Interlacing in Controllers Implementation: Frequency Analysis

TL;DR

The paper tackles implementing LTI controllers in resource-constrained environments by interlacing fast and slow poles to reduce computation while preserving performance. It develops a discrete lifting framework for dual-rate systems and introduces polynomial transformations to obtain slow-term blocks, enabling a lifted LPV-like modeling of interlaced controllers. A dual-rate frequency response methodology is provided to extract component frequencies and assess ripple, phase margin, and bandwidth in the interlaced setup, with guidance on input–output strategies. A practical design example demonstrates the approach, highlighting trade-offs such as chattering and noise sensitivity, and establishing a workflow for choosing interlacing configurations in real implementations.

Abstract

The main goal of this contribution is to explain how to use interlacing techniques for LTI controllers implementation and analyze different struc- tures in this environment. These considerations lead to an important com- putation saving in constrained resource environments. It has been also intro- duced new procedures for obtaining the blocks related to different real and complex controllers poles. The resultant time-varying system is modeled using proper discrete lifting techniques and a new and efficient dual-rate fre- quency response computation allows to determine the characteristics of the control loop with interlaced controller. Examples illustrate the theoretical proposals.

Figures (6)

• Figure 1: Interlacing. Basic Procedure
• Figure 2: Closed Loop Output Response with different Blocks order. Fast Input-Fast output
• Figure 3: Closed Loop Output Response with different Strategies Input - Output
• Figure 4: Closed Loop Output Response Comparison with Single Rate Controllers
• Figure 5: Dual-Rate Bode diagrams with different Input - Output strategies