In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips

TL;DR

The paper addresses generating true random numbers without dedicated hardware by exploiting simultaneous multi-row activation (SiMRA) in commercial DRAM. It presents an extensive experimental study over $96$ DDR4 chips to quantify how entropy, latency, and throughput vary with activated-row count ($2$, $4$, $8$, $16$, $32$), data patterns, temperature, and subarray location, releasing open-source tooling. The authors introduce SiMRA-TRNG, a four-bank design that initializes rows via RowClone-like operations, uses APA to generate entropy, and post-processes with SHA-256, achieving high throughput while passing the NIST STS tests. Key findings show that entropy generally increases with the number of activated rows but is strongly influenced by temperature and data pattern, underscoring the need for careful parameter selection; the work delivers a practical, open platform for DRAM-based randomness generation with higher throughput than prior state-of-the-art approaches.

Abstract

In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chips by leveraging simultaneous multiple-row activation (SiMRA) via an extensive characterization of 96 DDR4 DRAM chips. We rigorously analyze SiMRA's true random generation potential in terms of entropy, latency, and throughput for varying numbers of simultaneously activated DRAM rows (i.e., 2, 4, 8, 16, and 32), data patterns, temperature levels, and spatial variations. Among our 11 key experimental observations, we highlight four key results. First, we evaluate the quality of our TRNG designs using the commonly-used NIST statistical test suite for randomness and find that all SiMRA-based TRNG designs successfully pass each test. Second, 2-, 8-, 16-, and 32-row activation-based TRNG designs outperform the state-of-theart DRAM-based TRNG in throughput by up to 1.15x, 1.99x, 1.82x, and 1.39x, respectively. Third, SiMRA's entropy tends to increase with the number of simultaneously activated DRAM rows. Fourth, operational parameters and conditions (e.g., data pattern and temperature) significantly affect entropy. For example, for most of the tested modules, the average entropy of 32-row activation is 2.51x higher than that of 2-row activation. For example, increasing the temperature from 50°C to 90°C decreases SiMRA's entropy by 1.53x for 32-row activation. To aid future research and development, we open-source our infrastructure at https://github.com/CMU-SAFARI/SiMRA-TRNG.

Figures (10)

• Figure 1: DRAM organization. Adapted from orosa2021deeper.
• Figure 2: Our DRAM Bender olgun2023dram based experimental setup.
• Figure 3: Our laboratory for real DRAM chip experiments.
• Figure 4: Two example data layouts for 2-row activation with (a) data pattern 01 and (b) data pattern 10.
• Figure 5: Command sequence for true random number generation in COTS DRAM chips using and the state of cells during each related step.