HHEML: Hybrid Homomorphic Encryption for Privacy-Preserving Machine Learning on Edge

TL;DR

This paper introduces HHEML, a hardware-accelerated hybrid homomorphic encryption framework for privacy-preserving machine learning on edge devices. It hardware-accelerates the Pasta-based symmetric encryption on an FPGA (PYNQ-Z2) and offloads the homomorphic workload to a server-side GuardML stack via Ethernet, forming an end-to-end PPML pipeline. Key contributions include a PS-PL co-designed architecture, a two-XOF pipeline to halve encryption rounds for large inputs, and a full PPML workflow that significantly reduces client latency while maintaining security. Experimental results on MNIST show over $50\times$ reduction in client encryption latency and about a $2\times$ improvement in hardware throughput compared with prior FPGA-based HHE accelerators, with end-to-end latency reductions from hundreds of milliseconds to single-digit milliseconds. The work demonstrates the practicality of low-power, hardware-accelerated HHE for edge deployment and provides a methodology for scalable hardware-software co-design in resource-constrained privacy-preserving ML systems.

Abstract

Privacy-preserving machine learning (PPML) is an emerging topic to handle secure machine learning inference over sensitive data in untrusted environments. Fully homomorphic encryption (FHE) enables computation directly on encrypted data on the server side, making it a promising approach for PPML. However, it introduces significant communication and computation overhead on the client side, making it impractical for edge devices. Hybrid homomorphic encryption (HHE) addresses this limitation by combining symmetric encryption (SE) with FHE to reduce the computational cost on the client side, and combining with an FHE-friendly SE can also lessen the processing overhead on the server side, making it a more balanced and efficient alternative. Our work proposes a hardware-accelerated HHE architecture built around a lightweight symmetric cipher optimized for FHE compatibility and implemented as a dedicated hardware accelerator. To the best of our knowledge, this is the first design to integrate an end-to-end HHE framework with hardware acceleration. Beyond this, we also present several microarchitectural optimizations to achieve higher performance and energy efficiency. The proposed work is integrated into a full PPML pipeline, enabling secure inference with significantly lower latency and power consumption than software implementations. Our contributions validate the feasibility of low-power, hardware- accelerated HHE for edge deployment and provide a hardware- software co-design methodology for building scalable, secure machine learning systems in resource-constrained environments. Experiments on a PYNQ-Z2 platform with the MNIST dataset show over a 50x reduction in client-side encryption latency and nearly a 2x gain in hardware throughput compared to existing FPGA-based HHE accelerators.

Figures (4)

• Figure 1: The Workflow of an HHE-based PPML System
• Figure 2: HHEML System Overview
• Figure 3: HHEML Workflow
• Figure 4: XOF pipeline design