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Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads

Mukul Lokhande, Narendra Singh Dhakad, Seema Chouhan, Akash Sankhe, Santosh Kumar Vishvakarma

TL;DR

Res-DPU advances edge-AI compute by delivering a resource-shared digital PIM unit with a transistor-efficient per-bit multiply ($5.25T$) and a reduced-adder-tree TRAIT design, enabling higher density and lower power. The CIA2M method provides runtime accuracy-latency trade-offs without extra error-correction circuitry, achieving 3-cycle approximate and 4-cycle accurate modes with minimal loss. The 16 KB REP-DPIM macro achieves up to $0.43$ TOPS and $87.22$ TOPS/W with pruning, while maintaining a QoR of $96.85%$ on CIFAR-10 for ResNet-18 and VGG-16, demonstrating strong edge-accelerator suitability. Collectively, these contributions offer a scalable, energy-efficient path toward integrating PIM as a near-memory compute unit, potentially as L3 cache in future SoCs.

Abstract

Processing-in-memory (PIM) has emerged as the go to solution for addressing the von Neumann bottleneck in edge AI accelerators. However, state-of-the-art (SoTA) digital PIM approaches suffer from low compute density, primarily due to the use of bulky bit cells and transistor-heavy adder trees, which impose limitations on macro scalability and energy efficiency. This work introduces Res-DPU, a resource-shared digital PIM unit, with a dual-port 5T SRAM latch and shared 2T AND compute logic. This reflects the per-bit multiplication cost to just 5.25T and reduced the transistor count of the PIM array by up to 56% over the SoTA works. Furthermore, a Transistor-Reduced 2D Interspersed Adder Tree (TRAIT) with FA-7T and PG-FA-26T helps reduce the power consumption of the adder tree by up to 21.35% and leads to improved energy efficiency by 59% compared to conventional 28T RCA designs. We propose a Cycle-controlled Iterative Approximate-Accurate Multiplication (CIA2M) approach, enabling run-time accuracy-latency trade-offs without requiring error-correction circuitry. The 16 KB REP-DPIM macro achieves 0.43 TOPS throughput and 87.22 TOPS/W energy efficiency in TSMC 65nm CMOS, with 96.85% QoR for ResNet-18 or VGG-16 on CIFAR-10, including 30% pruning. The proposed results establish a Res-DPU module for highly scalable and energy-efficient real-time edge AI accelerators.

Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads

TL;DR

Res-DPU advances edge-AI compute by delivering a resource-shared digital PIM unit with a transistor-efficient per-bit multiply () and a reduced-adder-tree TRAIT design, enabling higher density and lower power. The CIA2M method provides runtime accuracy-latency trade-offs without extra error-correction circuitry, achieving 3-cycle approximate and 4-cycle accurate modes with minimal loss. The 16 KB REP-DPIM macro achieves up to TOPS and TOPS/W with pruning, while maintaining a QoR of on CIFAR-10 for ResNet-18 and VGG-16, demonstrating strong edge-accelerator suitability. Collectively, these contributions offer a scalable, energy-efficient path toward integrating PIM as a near-memory compute unit, potentially as L3 cache in future SoCs.

Abstract

Processing-in-memory (PIM) has emerged as the go to solution for addressing the von Neumann bottleneck in edge AI accelerators. However, state-of-the-art (SoTA) digital PIM approaches suffer from low compute density, primarily due to the use of bulky bit cells and transistor-heavy adder trees, which impose limitations on macro scalability and energy efficiency. This work introduces Res-DPU, a resource-shared digital PIM unit, with a dual-port 5T SRAM latch and shared 2T AND compute logic. This reflects the per-bit multiplication cost to just 5.25T and reduced the transistor count of the PIM array by up to 56% over the SoTA works. Furthermore, a Transistor-Reduced 2D Interspersed Adder Tree (TRAIT) with FA-7T and PG-FA-26T helps reduce the power consumption of the adder tree by up to 21.35% and leads to improved energy efficiency by 59% compared to conventional 28T RCA designs. We propose a Cycle-controlled Iterative Approximate-Accurate Multiplication (CIA2M) approach, enabling run-time accuracy-latency trade-offs without requiring error-correction circuitry. The 16 KB REP-DPIM macro achieves 0.43 TOPS throughput and 87.22 TOPS/W energy efficiency in TSMC 65nm CMOS, with 96.85% QoR for ResNet-18 or VGG-16 on CIFAR-10, including 30% pruning. The proposed results establish a Res-DPU module for highly scalable and energy-efficient real-time edge AI accelerators.
Paper Structure (10 sections, 2 equations, 7 figures, 2 tables)

This paper contains 10 sections, 2 equations, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Prior Works & Motivation:
  3. Resource-efficient, Enhanced Performance Flexible DPIM (REP-DPIM) macro
  4. Cycle-controlled Iterative Approximate-Accurate Multiplication (CIA2M) Approach
  5. Resource-shared DPU (Res-DPU) and sub-bank (SBNK)
  6. Transistor-Reduced 2D Interspersed Adder Tree
  7. Performance Analysis and Mapping Strategy
  8. Hardware Analysis
  9. Mapping Strategy & Accuracy Evaluation
  10. Conclusion

Figures (7)

  • Figure 1: Visualisation of Error values (x-axis) against no of occurrences (y-axis) for the proposed CIA2M compared to accurate INT-8b multiplication over all possible (65536) cases.
  • Figure 2: Data-path circuit comparison of Flex-DPU Flex-DCIM_TCASI'25 and Res-DPU, highlighting reduced transistor count.
  • Figure 3: Proposed 8x4 sub-bank for 8-bit CIA2M , contributes up-to two times MAC throughput compared to Flex-SBLKFlex-DCIM_TCASI'25.
  • Figure 4: Illustrations of the proposed Res-DPU Macro Architecture
  • Figure 5: Fundamentals components of Transistor-reduced 2D-Interspersed Adder Tree (TRAIT), (a) PG-26T and (b) FA-7T.
  • ...and 2 more figures