Chip-to-chip hyperentanglement distribution and entanglement purification using silicon integrated photonics

TL;DR

This work addresses the challenge of scalable quantum repeaters by demonstrating chip-to-chip hyperentanglement distribution and entanglement purification entirely on silicon photonics. It combines path-encoded high-dimensional entanglement on-chip with fiber-based polarization-spatial hyperentanglement via 2D grating couplers and implements a deterministic on-chip purification circuit that uses a waveguide-crossing CNOT-like operation to purify the polarization qubit, consuming the spatial degree of freedom. The results show significant fidelity and CHSH improvements under BF and PF noise, with key numbers such as $F$ rising from $0.738$ to $0.848$ and $S$ from $1.898$ to $2.195$, validating the viability of integrated purification for quantum repeater architectures. The work highlights the potential of CMOS-compatible silicon photonics to enable large-scale, stable, and manufacturable quantum networks by integrating entanglement generation, purification, phase stabilization, and linking with swapping and memory components on a single platform.

Abstract

Quantum repeaters are employed in quantum communication to overcome the long-distance transmission loss of quantum states. The quantum repeater is based on various key technologies, including quantum entanglement swapping, quantum memory, and entanglement purification. In particular, quantum purification can distil high-quality entanglement from the degraded entangled states which is propagating through noisy quantum communication channels. Although previous reports have demonstrated on-chip entanglement swapping and teleportation through the less-noisy channel, current entanglement purification experiments still rely on off-chip discrete devices, leading to limitations on scalability, stability, and controllability. In this paper, for the first time, we demonstrated chip-to-chip hyperentanglement distribution and quantum entanglement purification based on integrated silicon chips. Path-encoded high-dimensional entangled photon pairs are produced on the chip, converted to fibre-based polarization-spatial hyperentanglement by grating couplers, distributed to the receiver silicon chip, and finally purified by consuming the spatial degree of freedom. Our purification scheme by integrated photonics finished the last puzzle of on-chip quantum repeater, which will promote the realization of the quantum repeater based on integrated photonics.

Figures (13)

• Figure 1: The chip-based entanglement purification schematic and chip layout. (a) Schematic of chip-based entanglement purification using hyperentanglement. The hyperentanglement source chip (Charlie) generates polarization-spatial-mode entangled photons, which are distributed to chip Alice and chip Bob. On chips Alice and Bob, the deterministic CNOT operations are implemented. After passing through the purification circuits on chips Alice and Bob, the entanglement fidelity of the polarization qubit is expected to be improved. (b) Schematic of chip Alice/Charlie. The integrated circuit on this silicon chip is responsible for entanglement generation, purification of signal photons (blue), and waveguide-to-fiber coupling of the idler photons (red). The pump pulses (green) are distributed into four snake-shaped waveguides where spontaneous four-wave mixing (SFWM) occurs. Only one photon pair is generated in four waveguides, and then demultiplexed by asymmetric MZIs composed of multimode interferometers (MMIs) and phase shifters. The 'PF EGC’ represents the phase-flip error generation circuit, and the 'BF EGC’ represents the bit-flip error generation circuit. The purification section consists of four reconfigurable waveguide crossings. For the idler photons, they are converted into polarization-spatial-mode entangled photons in fibers by the 2D grating coupler (2D GC). (c) Schematic of chip Bob. The pump and idler photons are coupled into the chip through the 2D GC. With the 2D GC, the polarization-spatial-mode encoded photons in fiber are converted back into path-encoded photons on chip. The first four MZIs act as mode attenuators to compensate for the different losses of the four optical paths and to split part of the pump into the central MMI of the phase monitor circuit. Here, about 11% of the pump from the two fibers is directed into the phase monitor to interfere, converting the relative phase difference between the two fibers into a power difference at the outputs of this MMI.
• Figure 2: The experimental setup for chip-to-chip hyperentanglement distribution and chip-based entanglement purification. Both silicon chips (chip Alice/Charlie and chip Bob) are optically and electrically packaged. Optical signals are coupled through single-mode fiber arrays to the GCs on both chips, and electrical control is provided via electrical cables. All cables are connected to a 96-channel digital-to-analog converter (DAC), which enables independent phase tuning of the heaters and reconfiguration of all the MZIs on both silicon chips. Each chip is also packaged with a thermoresistor and a thermoelectric cooler (TEC), allowing temperature stabilization through a TEC controller. The detection efficiency of the superconducting nanowire single-photon detectors (SNSPDs) is about 90%, and the dark count rate and background noise are around 200 Hz.
• Figure 3: Reconfigurable integrated circuits for noise simulation and purification demonstration in this work. (a) Hadamard gate circuit for the signal photon. (b) Phase-flip error generation circuit (PF EGC) and bit-flip error generation circuit (BF EGC) for the idler photon. ODL, PS, and on-chip mode attenuators are omitted in this figure for clarity. (c) (f) Reconfigured PF EGC for the cases of no error (c), PF error on the polarization degree of freedom (DOF) (d), PF error on the spatial-mode DOF (e), and PF errors on both degrees of freedom (f). (g) (j) Reconfigured BF EGC for the cases of no error (g), BF error on the polarization DOF (h), BF error on the spatial-mode DOF (i), and BF errors on both DOFs (j). (k) Reconfigured Hadamard gate circuit used for PF error purification. (l) (n) Purification demonstration circuits for purification off with polarization QST (l), purification off with spatial QST (m), and purification on with polarization QST (n). (o) Original purification demonstration circuit constructed from five MZIs. (p) Measured density matrices of polarization and spatial-mode qubits for the distributed hyperentangled states.
• Figure 4: QST results before and after purification. (a) Density matrices of the polarization qubit and spatial-mode qubit before purification with a 20% BF error rate. (b) Density matrices of the polarization qubit after purification under a 20% BF error rate. (c) Density matrices of the polarization qubit and spatial-mode qubit before purification with a 20% PF error rate. (d) Density matrices of the polarization qubit after purification under a 20% PF error rate.
• Figure S1: The wire-bonded chip Charlie/Alice (a) and Bob (b). The electrical wires connect the pads on the chip to the pads on the PCB. The fiber array is aligned with the grating couplers on the chip and glued on chip, with all 2D GCs positioned on the left side and all 1D GCs on the right side.