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On-Chip Time-Multiplexed Electronic Control of a Silicon Photonic Coherent Adder for Communication and Sensing

Samuele De Gaetano, Monica Crico, Giorgio Ferrari, Marco Sampietro, Francesco Morichetti, Andrea Melloni, Francesco Zanetto

TL;DR

This work addresses the wiring bottleneck in large programmable PICs by integrating electronics on the silicon photonic chip and employing a time-multiplexed control scheme. It combines a 2-stage MZI switch matrix with a 4×1 coherent adder and on-chip MUX/DEMUX, enabling real-time readout and heater actuation with memory, while reducing external I/O to a minimal set and leveraging $\\log_2(N_D)$ addressing. The authors validate the approach on a silicon photonic coherent adder, achieving rapid reconfiguration and stable joint communication and sensing: 25 Gbps data transmission alongside real-time phase-difference measurement, with only ~0.55 dB penalty compared to a reference. The results highlight scalable control for large PICs, enabling simultaneous communication and sensing applications with simplified packaging and wiring.

Abstract

The growing complexity of reconfigurable photonic circuits, made possible by the established maturity of silicon photonic foundries, demands efficient strategies to monitor and actively control the optical functionality at runtime. In this work, we show that both the readout of integrated sensors and the driving of actuators can be performed with a time-multiplexed addressing scheme, that drastically reduces the number of electrical connections required to interface the chip to the external hardware. This approach is achieved by monolithically integrating the electronic circuits needed to serialize/deserialize the feedback action directly on the photonic chip. We experimentally validate the proposed strategy with a silicon photonic coherent adder, showing that such time-multiplexed control does not introduce any penalty in the optical functionality. The circuit operation is then validated in a joint communication and sensing scenario, where the coherent adder is used to simultaneously receive a 25 Gbps high-speed transmission and to measure the phase difference between the input light beams.

On-Chip Time-Multiplexed Electronic Control of a Silicon Photonic Coherent Adder for Communication and Sensing

TL;DR

This work addresses the wiring bottleneck in large programmable PICs by integrating electronics on the silicon photonic chip and employing a time-multiplexed control scheme. It combines a 2-stage MZI switch matrix with a 4×1 coherent adder and on-chip MUX/DEMUX, enabling real-time readout and heater actuation with memory, while reducing external I/O to a minimal set and leveraging addressing. The authors validate the approach on a silicon photonic coherent adder, achieving rapid reconfiguration and stable joint communication and sensing: 25 Gbps data transmission alongside real-time phase-difference measurement, with only ~0.55 dB penalty compared to a reference. The results highlight scalable control for large PICs, enabling simultaneous communication and sensing applications with simplified packaging and wiring.

Abstract

The growing complexity of reconfigurable photonic circuits, made possible by the established maturity of silicon photonic foundries, demands efficient strategies to monitor and actively control the optical functionality at runtime. In this work, we show that both the readout of integrated sensors and the driving of actuators can be performed with a time-multiplexed addressing scheme, that drastically reduces the number of electrical connections required to interface the chip to the external hardware. This approach is achieved by monolithically integrating the electronic circuits needed to serialize/deserialize the feedback action directly on the photonic chip. We experimentally validate the proposed strategy with a silicon photonic coherent adder, showing that such time-multiplexed control does not introduce any penalty in the optical functionality. The circuit operation is then validated in a joint communication and sensing scenario, where the coherent adder is used to simultaneously receive a 25 Gbps high-speed transmission and to measure the phase difference between the input light beams.
Paper Structure (10 sections, 3 equations, 9 figures)

This paper contains 10 sections, 3 equations, 9 figures.

Figures (9)

  • Figure 1: a) Schematic of the complete silicon chip (blue area), connected to the external control electronics (green area). The electrical signals needed to read the PDs and drive the heaters are serialized and deserialized with on-chip electronic circuits. b) Microscope photograph of the chip, highlighting the electronic and photonic sections. The chip has been manufactured by a commercial Silicon Photonics foundry AMF, without modifications to the conventional fabrication process.
  • Figure 2: Time-multiplexed algorithm for sequential a) readout of multiple monitor PDs and b) driving of the on-chip thermal actuators. Reading and driving are cycled continuously and automatically.
  • Figure 3: Schematic of the time-multiplexed digital control feedback loop employed for configuring and locking the optical functionality of the PIC.
  • Figure 4: a) Schematic of the optical setup employed for validating the PIC functionality, the (de)multiplexers and the control strategy. b) Photograph of the PIC mounted and wire-bonded to the interface electronic board. All the fibers are single-mode.
  • Figure 5: Measured transfer function of a MZI (blue) and its first derivative (red) obtained with the dithering technique. The stationary points of the MZI transfer function correspond to the zeros of the first derivative.
  • ...and 4 more figures