Impact of Switching Layer Architecture on Power Consumption in RRAM

TL;DR

This paper addresses the power efficiency of planar resistive memories by comparing traditional compact thin-film WOx with porous glancing-angle deposited (GLAD) helical WOx in ITO/WOx/ITO stacks. The authors systematically vary active-layer thickness (50–200 nm) and operate devices at a high current limit (5 mA) and a reduced limit (500 μA) to reveal geometry-driven switching behavior. They find that porous helices support reproducible switching at 500 μA with substantial reductions in RESET voltage and switching currents, yielding up to ~89% SET and ~83% RESET power reductions and a memory-window increase from ~7 to ~44 (about 5–7×). The results indicate that geometry-induced field concentration and confinement enhance low-power operation and read margin, presenting a design principle for energy-efficient, high-margin RRAM and motivating exploration of high-surface-area materials for transparent and flexible electronics.

Abstract

This work demonstrates that porous helical WOx architectures enable a distinct low-power regime for planar ITO/WOx/ITO resistive random-access devices. While thin film and helical devices behave similarly at a 5 mA compliance, only helical devices sustain reproducible operation at 500 uA, where RESET voltages reduce by ~60%, switching currents decrease by 68-75%, and SET/RESET power drops by ~89% and ~83%. With helical devices operating at 500 uA, the memory window expands 400-600% due to selective suppression of high-resistive-state leakage, yielding both lower-power and improved read margin in a regime inaccessible to thin film devices. These results highlight geometry-driven field enhancement and confinement as practical design principles for low-power, high-margin resistive memories and point toward opportunities in transparent, flexible, and high-surface-area material systems.

Figures (13)

• Figure 1: Schematic cross-section of the TF device stack. Vertical thicknesses are not drawn to scale, and the schematic is intended only to illustrate the layer sequence and lateral electrode geometry.
• Figure 2: Model of a helix with parameters: length ($L$), pitch ($p$), helix diameter ($d$), and rod thickness ($2r$).
• Figure 3: Top-view SEM image of the porous helical WO$_x$ active-layer.
• Figure 4: SEM top-view of porous helical WO$_x$ devices.
• Figure 5: Bipolar I-V characteristic of a typical $500$$\mu$A CCL helical device cycle. Electroforming, SET, and RESET processes are indicated, with corresponding $V_{\text{SET}}$ and $V_{\text{RESET}}$. HRS and LRS are indicated by $\times$ markers at a non-disturbing read bias of $0.1$ V.