Quantum Reverse Mapping: Synthesizing an Optimal Spin Qubit Shuttling Bus Architecture for the Surface Code

TL;DR

This work tackles robust logical-qubit encoding on a rotated surface code by designing a ground-up, one-dimensional spin-qubit shuttling-bus architecture through Quantum Reverse Mapping. It combines an exact MILP for small code distances with a scalable Zig-Zag heuristic to minimize shuttling distance and cycle latency, prioritizing time over distance to accommodate dephasing in silicon spins. Architectural synthesis is validated against full Stim simulations under realistic noise, achieving logical error rates as low as $2\cdot 10^{-10}$ per round at code distance $d=21$, demonstrating feasibility for scalable fault-tolerant spin-qubit processors. The framework provides a robust foundation for future heuristic compilation layers and can be extended to other QEC codes, highlighting the practicality of optimal encoding before scaling up quantum architectures.

Abstract

As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation techniques and heuristics to build on optimal or near-optimal layouts, improving scalability and error resilience. In this work, we synthesize a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling. We formulate a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and propose a scalable heuristic that matches optimal results while maintaining linear computational complexity. We evaluate the synthesized architecture using architectural metrics, such as shuttling distance and cycle time, and full quantum simulations under realistic noise models, showing that the proposed design can sustain logical error rates as low as $2\cdot 10^{-10}$ per round at code distance 21, showcasing its feasibility for scalable quantum error correction in spin-based quantum processors.

Figures (21)

• Figure 1: Sketch of the proposed shuttling bus architecture. Spins in quantum dots $\{ Q_0, \ldots, Q_n \}$ are shuttled to manipulation zones $\{ O_0, \ldots, O_n \}$ when they have to interact. The distance between consecutive elements in the 1D shuttling bus is $d_{qu}$, and the shuttling velocity of the spins is set to $v_{sh}$.
• Figure 2: The 2D planer layout of the distance-3 surface code (top). Data qubits are represented with white nodes and $X$ and $Z$ checks are red and blue nodes respectively. Middle and bottom circuits are Z- and X-syndrome extraction circuits, respectively, each consisting on four CNOT gates.
• Figure 3: Check interaction order to avoid hook (or horizontal) errors. Note that the two figures have equivalent interactions order, depending on whether seen from the check/ancilla or the data qubits point of view. Numbers reference CNOT order as in Figure \ref{['fig:surface_code_3']}.
• Figure 4: Composite interaction order for the data qubits in the distance-3 surface code lattice. Composite interaction order for the data qubits in the distance-3 surface code lattice. Empty, dashed qubits are shown at the patch boundaries to illustrate how the interaction structure extends when scaling to larger code distances.
• Figure 5: Each data qubit's interactions for each syndrome extraction slice in the distance-3 surface code.