Real-Time Readout System Design for the BULLKID-DM Experiment: Enhancing Dark Matter Search Capabilities

TL;DR

The paper tackles the challenge of detecting low-mass dark matter by developing a real-time, room-temperature readout for cryogenic MKIDs in the BULLKID-DM experiment. It presents a RFSoC-based DAQ architecture with frequency-division multiplexing, a modular firmware chain (tone generation, channelization, triggering), and integrated calibration features, validated on a three-wafer demonstrator. Key contributions include hardware and firmware design, a dedicated build system (SoCks), automatic resonator detection/characterization, phase-rotation techniques for triggering, and energy calibration integration. The work demonstrates scalable, low-noise readout capable of handling >2000 detectors across 16 cryogenic lines, enabling a practical path toward large-scale, low-threshold dark matter searches at underground facilities like Gran Sasso.

Abstract

The BULLKID-DM experiment aims to detect WIMP-like potential Dark Matter particles with masses below 1 GeV/c^2. Sensing these particles is challenging, as it requires nuclear recoil detectors characterized by high exposure and an energy threshold in the order of 100 eV, thus exceeding the capabilities of conventional semiconductor detectors. BULLKID-DM intends to tackle this challenge by using cryogenic Kinetic Inductance Detectors (MKIDs) with exceptional energy thresholds to sense a target with a total mass of 800 g across 16 wafers, divided into over 2000 individually instrumented silicon dice. The MKIDs on each wafer are coupled to a single transmission line and read using a frequency division multiplexing approach by the room-temperature data acquisition. In this contribution, we describe and assess the design of the room-temperature readout electronics system, including the selected hardware components and the FPGA firmware which contains the real-time signal processing stages for tone generation, frequency demultiplexing, and event triggering. We evaluate the system on the ZCU216 board, a commercial evaluation card built around a Radio-Frequency System-on-Chip (RFSoC) with integrated high-speed DACs and ADCs, and connected it to a custom-designed analog front-end for signal conditioning.

Figures (7)

• Figure 1: BULLKID-DM DAQ system setup. The 19-inch rack-mounted enclosure houses the ZCU216 evaluation board with the custom front-end, along with the power supply unit, cooling fans, cabling, and accessories.
• Figure 2: Block diagram of the firmware implemented on the rfsoc. The upper section illustrates the real-time processing chain running on the pl, while the logging and the custom Servicehub software for user interaction are implemented on the ps part of the soc.
• Figure 3: Configuration of the converters within the rfdc IP core of the rfsoc. All 16 converter channels are configured equally and share a common input reference clock.
• Figure 4: Block diagram of the full digital channelization stage. It converts the wideband input signal from the adc containing the modulated frequency comb into a time-division multiplexed data stream containing the reconstructed and separated detector signals.
• Figure 5: Projected resource estimation on the pl for up to 16 processing chains. The offset in LUTs and BRAM resources results from the implementation of the storage module, whose size is independent of the number of readout chains.