ReLACE: A Resource-Efficient Low-Latency Cortical Acceleration Engine

TL;DR

The paper targets resource-constrained edge AI by combining a neuromorphic SNN approach with a modular CORDIC-based Hodgkin-Huxley neuron to reduce hardware and latency. It introduces the Cortical Neural Pool (CNP) and demonstrates that the RCHH neuron achieves $24.5\%$ LUT reduction, $70\%$ NRMSE improvement, and $35.2\%$ speedup, with the CNP delivering $2.85\times$ throughput (12.69 GOPS) and only $0.35\%$ MNIST accuracy loss against a DNN baseline. FPGA experiments on VC707 show significant resource and performance advantages over iso-functional DNN engines and prior SNN accelerators, supporting the viability of edge-focused neuromorphic accelerators. The work advances toward practical, low-power SNN hardware, with future aims to scale to deeper architectures and evaluate autonomous driving applications.

Abstract

We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC-based Hodgkin Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. The FPGA implementation of the RCHH neuron shows 24.5% LUT reduction and 35.2% improved speed, compared to SoTA designs, with 70% better normalised root mean square error (NRMSE). Furthermore, the CNP exhibits 2.85x higher throughput (12.69 GOPS) compared to a functionally equivalent CORDIC-based DNN engine, with only a 0.35% accuracy drop compared to the DNN counterpart on the MNIST dataset. The overall results indicate that the design shows biologically accurate, low-resource spiking neural network implementations for resource-constrained edge AI applications.

Figures (6)

• Figure 1: Visualisation depicting SNN use cases in wearable devices, emphasis on resource-constrained implementation, adapted from Neuromorphic_accl
• Figure 2: Architecture for DNN accelerator engineDNN_Retro'25 showing internal structure of NeuronDNN_TRETS'23.
• Figure 3: (a) Architecture for the Spiking neuronal pool, functional equivalent of DNN neuron engine for the execution of AI workloads with RCHH Neuron, (b) Complete top-Level FSM of a single neuron, showing different neuron states.
• Figure 4: Diverse spiking characteristics generated by the HE-HH model. Top: Fast Spiking: High-frequency non-adapting spikes (e.g., cortical interneurons), Intrinsically Bursting: Spike clusters followed by hyperpolarisation (e.g., thalamic neurons), Chattering: Gamma-frequency oscillations (30–80 Hz) during sustained input. Bottom: Low-Threshold Spiking: Subthreshold oscillations leading to delayed firing, Tonic/Rebound Spiking: Persistent firing post-inhibitory input (e.g., thalamocortical cells).
• Figure 5: Network implementation, with only 0.35% accuracy drop; Input layer of $784$ neurons receives $784$ rate-coded spike train values from every $28 \times 28$ MNIST image. These, multiplied with the synaptic weights (learned through STDP), produce $I_{\text{inj}}$ for the neurons; these neurons then go on to spike with the input polarisation, producing output spikes to the postsynaptic neuron, which does the same process and finally predicts the digit (maximum spikes among the final 10 classes).