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SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

Chengxi Li, Yang Sun, Lei Chen, Yiwen Wang, Mingxuan Yuan, Evangeline F. Y. Young

TL;DR

This work tackles RTL-level optimization of multiplexer trees, where traditional tools like Yosys miss deeper logical dependencies between signals. It introduces smaRTLy, which combines SAT-based redundancy elimination on bounded sub-graphs with ADD-driven muxtree restructuring to aggressively reduce gate counts. Empirical results show an average of 8.95% extra AIG-area reduction on public IWLS-2005 and RISC-V benchmarks and up to 47.2% more reduction on industrial-scale designs, illustrating substantial real-world impact. The approach enhances PPA and can be integrated with other optimization passes to further improve RTL synthesis efficiency.

Abstract

This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and traditional tools like Yosys optimize them by traversing the tree and monitoring control port values. However, this method does not fully exploit the intrinsic logical relationships among signals or the potential for structural optimization. To address these limitations, we develop innovative strategies to remove redundant multiplexer trees and restructure the remaining ones, significantly reducing the overall gate count. We evaluate smaRTLy on the IWLS-2005 and RISC-V benchmarks, achieving an additional 8.95% reduction in AIG area compared to Yosys. We also evaluate smaRTLy on an industrial benchmark in the scale of millions of gates, results show that smaRTLy can remove 47.2% more AIG area than Yosys. These results demonstrate the effectiveness of our logic inferencing and structural rebuilding techniques in enhancing the RTL optimization process, leading to more efficient hardware designs.

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

TL;DR

This work tackles RTL-level optimization of multiplexer trees, where traditional tools like Yosys miss deeper logical dependencies between signals. It introduces smaRTLy, which combines SAT-based redundancy elimination on bounded sub-graphs with ADD-driven muxtree restructuring to aggressively reduce gate counts. Empirical results show an average of 8.95% extra AIG-area reduction on public IWLS-2005 and RISC-V benchmarks and up to 47.2% more reduction on industrial-scale designs, illustrating substantial real-world impact. The approach enhances PPA and can be integrated with other optimization passes to further improve RTL synthesis efficiency.

Abstract

This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and traditional tools like Yosys optimize them by traversing the tree and monitoring control port values. However, this method does not fully exploit the intrinsic logical relationships among signals or the potential for structural optimization. To address these limitations, we develop innovative strategies to remove redundant multiplexer trees and restructure the remaining ones, significantly reducing the overall gate count. We evaluate smaRTLy on the IWLS-2005 and RISC-V benchmarks, achieving an additional 8.95% reduction in AIG area compared to Yosys. We also evaluate smaRTLy on an industrial benchmark in the scale of millions of gates, results show that smaRTLy can remove 47.2% more AIG area than Yosys. These results demonstrate the effectiveness of our logic inferencing and structural rebuilding techniques in enhancing the RTL optimization process, leading to more efficient hardware designs.
Paper Structure (7 sections, 2 theorems, 7 figures, 3 tables, 1 algorithm)

This paper contains 7 sections, 2 theorems, 7 figures, 3 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. SAT-based Redundancy Elimination
  3. Muxtree Restructuring
  4. Experiment
  5. Public Benchmarks
  6. Industrial Benchmarks
  7. Conclusions

Key Result

Theorem 1

In the RTL level circuit, a signal $S$ is possible to affect the value of signal $T$, only if:

Figures (7)

  • Figure 1: The multiplexer with the same control as the ancestor multiplexer can be optimized.
  • Figure 2: The data port with the same control signals as the ancestor multiplexer can be optimized.
  • Figure 3: The muxtree with different and logically dependent control signals.
  • Figure 4: The three situations where S(T) can affect T(S).
  • Figure 5: A muxtree for the $case$ statement in \ref{['list:case_statement']}. The muxtree is a chain.
  • ...and 2 more figures

Theorems & Definitions (4)

  • Theorem 1
  • proof
  • Theorem 2
  • proof