EEschematic: Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit

TL;DR

The paper addresses the need for interpretable analog circuit design by converting textual netlists into editable schematics using a multimodal large language model. It introduces EEschematic, which integrates SPICE netlists, natural language descriptions, circuit diagrams, and spatial JSON data, guided by a few-shot substructure library and Visual Chain-of-Thought prompts. Results on representative circuits show high structural correctness and good visual quality, illustrating the method's potential for scalable schematic generation. The work advances practical automatic schematic generation and provides a path toward integrating schematic design into ML-driven workflows.

Abstract

Circuit schematics play a crucial role in analog integrated circuit design, serving as the primary medium for human understanding and verification of circuit functionality. While recent large language model (LLM)-based approaches have shown promise in circuit topology generation and device sizing, most rely solely on textual representations such as SPICE netlists, which lack visual interpretability for circuit designers. To address this limitation, we propose EEschematic, an AI agent for automatic analog schematic generation based on a Multimodal Large Language Model (MLLM). EEschematic integrates textual, visual, and symbolic modalities to translate SPICE netlists into schematic diagrams represented in a human-editable format. The framework uses six analog substructure examples for few-shot placement and a Visual Chain-of-Thought (VCoT) strategy to iteratively refine placement and wiring, enhancing schematic clarity and symmetry. Experimental results on representative analog circuits, including a CMOS inverter, a five-transistor operational transconductance amplifier (5T-OTA), and a telescopic cascode amplifier, demonstrate that EEschematic produces schematics with high visual quality and structural correctness.

Figures (8)

• Figure 1: Different modalities of circuit representation, including natural language description, SPICE netlist, circuit schematic diagram, and corresponding position and wiring information within a JSON schema.
• Figure 2: The inner optimization loop for placement. The MLLM compares the current schematic with reference examples to determine whether modification is needed. If required, the model generates reasoning chains to guide schematic refinement. The updated schematic and its corresponding JSON data are then iteratively fed back into the inner optimization loop, enabling continuous improvement through multimodal reasoning.
• Figure 3: The complete process of schematic generation for the 5T-OTA from initial placement to the final result. Changes from previous iterations are highlighted in red blocks.
• Figure : (a) Best result
• Figure : (a) Best result