Phase gadget compilation of quantum circuits using multiqubit gates

TL;DR

The paper addresses hardware-aware quantum circuit compilation by introducing a phase-gadget framework that uses programmable multiqubit gates $U_\text{MQ}$ to implement all-to-all $Z\otimes Z$ couplings. It constructs a three-layer circuit with a middle phase-gadget layer, enabling significant depth reductions (approximately $15\times$) and drive-power reductions (about $4\times$) while improving implementation fidelity on benchmark circuits. Core contributions include efficient implementations of $G_Z$ and $G_X$ PGs via $U_\text{MQ}$, a left-handed $SU(4)$-based layering approach, and global optimization passes that iteratively minimize nuclear norm and gate counts. The approach is particularly well suited to trapped-ion platforms with long-range couplings and suggests that long-range all-to-all interactions can yield further speedups, especially when combined with Clifford-enhanced ancilla schemes. Overall, the method offers a practical route to faster, more robust quantum circuit execution on near-term and fault-tolerant hardware by leveraging phase gadgets and multiqubit entangling gates.

Abstract

Quantum circuit synthesis and compilation are critical components in the quantum computing stack, both for contemporary quantum systems, where efficient use of limited resources is essential, as well as for large-scale fault-tolerant platforms, where computation time can be minimized. The specific characteristics of the quantum hardware determine which circuit designs and optimizations are feasible. We present a phase-gadget based method for compilation of quantum circuits using programmable multiqubit entangling gates, that are native, among others, to trapped-ions quantum computers. We use phase-gadgets in order to generically reduce circuit depths and efficiently implement them with few, high-fidelity, multiqubit gates. We test our methods on a large set of benchmark circuits and demonstrate generic circuit depth reduction and implementation error reduction.

Figures (9)

• Figure 1: Implementation of phase gadgets using two multiqubit gates, $U_\text{MQ}$.
• Figure 2: Sketch of the proof of the PG merge identity in Eq. \ref{['eqPGmerge']}. The basic identity used is that the circuit $C_{Z_j\land Y_k}C_{X_j\land Y_k}$ can be implemented with a single two-qubit $Y\otimes Y$ gate (top), equivalent to a $Z\otimes Z$ gate. When consecutive $G_X$ and $G_Z$ PGs appear, the CNOT layer at their interface consists of multiple such instances (middle), this can be rearranged, and cast a single multiqubit gate (bottom).
• Figure 3: Top: Commutation rules examples for $Z$ phase gadgets. Bottom: Commutation rules examples for $X$ phase gadgets.
• Figure 4: Relative error reduction factor, according to Eq. \ref{['eqRelError']} (vertical). We consider various circuits for varying number of qubits, $N$ (horizontal), grouped by circuit type: Swap test (blue triangles), Ising model simulation (brown hexagons), Quantum phase estimation algorithm (red diamonds), Number multiplication (pink crosses), quantum Fourier transform (orange pentagons) and others (cyan squares, see caption). A generic relative error reduction of $\sim40\%$ is observed. A subset of circuits is tested with noise-injection and state simulation (green stars) showing an agreement with the other circuits.
• Figure 5: Two-qubit gate count to compiled multiqubit gate count ratio due to PG compilation (vertical, log-scale). We consider various circuits for varying number of qubits, $N$ (horizontal), grouped by circuit type as in Fig. \ref{['fig:rel_error']}. A generic gate count reduction of $\sim15$ is observed (reaching up to $\sim100$ in some cases). For Swap test (blue triangles), Ising model simulation (brown hexagons) and quantum Fourier transform (orange pentagons) performance clearly improves as $N$ increases.