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Electrical and Thermal Performance Tuning of Spoof Plasmonic Interconnect

Rafichha Yasmin, Ishrat Jahan, Abdelrahman Omar, Md. Zunaid Baten, A. B. M. Harun-ur Rashid, Soumitra Joy

TL;DR

The paper tackles the challenge of achieving high electrical bandwidth while maintaining thermal efficiency in dense chiplet interconnects. It introduces a compact, oxide-coated silicon SSPP interconnect with a meandered corrugated metal design that confines the signal to the metal surface, enabling broader bandwidth (about 0–5 GHz, ≈2.5× that of microstriplines) and reduced crosstalk. The study demonstrates that inserting a 50 μm SiO2 layer minimizes copper-related attenuation without sacrificing silicon’s superior heat dissipation, and reports significant thermal advantages over FR4 substrates. Collectively, the findings offer a viable, thermally efficient pathway for high-density interconnects in advanced packaging, supported by full-wave simulations across electromagnetic and thermal domains.

Abstract

This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for its superior thermal properties, and to counteract its high dielectric constant that typically causes high mutual capacitance among interconnects, we've engineered a periodically corrugated, compact metallic structure enabling signal propagation via strongly confined spoof surface plasmon polaritons (SSPPs). By placing this engineered metal on a $50$ $μ$m oxide layer atop Si substrate, we achieved a low insertion loss of $0.015$ dB/cm and a $10$ dB reduction in crosstalk noise within $5$ GHz, resulting in a bandwidth $2.5\times$ as high as that of a standard microstriplines of the same footprint. Furthermore, a $5$ ns input pulse showed minimal distortion and a $0.13$ ns/cm propagation delay in our proposed interconnect. Critically, the thin oxide layer minimally impacted the heat dissipation of Si substrate, demonstrating a fourfold reduction in temperature compared to an FR4 substrate. These full-wave simulation-supported findings present a viable pathway for high-density, thermally efficient interconnects in advanced packaging.

Electrical and Thermal Performance Tuning of Spoof Plasmonic Interconnect

TL;DR

The paper tackles the challenge of achieving high electrical bandwidth while maintaining thermal efficiency in dense chiplet interconnects. It introduces a compact, oxide-coated silicon SSPP interconnect with a meandered corrugated metal design that confines the signal to the metal surface, enabling broader bandwidth (about 0–5 GHz, ≈2.5× that of microstriplines) and reduced crosstalk. The study demonstrates that inserting a 50 μm SiO2 layer minimizes copper-related attenuation without sacrificing silicon’s superior heat dissipation, and reports significant thermal advantages over FR4 substrates. Collectively, the findings offer a viable, thermally efficient pathway for high-density interconnects in advanced packaging, supported by full-wave simulations across electromagnetic and thermal domains.

Abstract

This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for its superior thermal properties, and to counteract its high dielectric constant that typically causes high mutual capacitance among interconnects, we've engineered a periodically corrugated, compact metallic structure enabling signal propagation via strongly confined spoof surface plasmon polaritons (SSPPs). By placing this engineered metal on a m oxide layer atop Si substrate, we achieved a low insertion loss of dB/cm and a dB reduction in crosstalk noise within GHz, resulting in a bandwidth as high as that of a standard microstriplines of the same footprint. Furthermore, a ns input pulse showed minimal distortion and a ns/cm propagation delay in our proposed interconnect. Critically, the thin oxide layer minimally impacted the heat dissipation of Si substrate, demonstrating a fourfold reduction in temperature compared to an FR4 substrate. These full-wave simulation-supported findings present a viable pathway for high-density, thermally efficient interconnects in advanced packaging.
Paper Structure (7 sections, 8 figures)

This paper contains 7 sections, 8 figures.

Table of Contents

  1. Introduction
  2. Theory and Device Structure
  3. Result And Discussion
  4. Electromagnetic Insertion Loss
  5. Cross-talk Noise
  6. Thermal Analysis
  7. Conclusion

Figures (8)

  • Figure 1: (a) A double sided, mirror symmetric SSPP waveguide (b) A compact design of double sided SSPP waveguide proposed in this work, we name it as meandered SSPP
  • Figure 2: Frequency vs longitudinal phase dispersion relation for a unit cell of SSPP metal wire with ground plane, shown in the inset, and that for a microstripline for two different substrate materials: FR4 Epoxy and Silicon.
  • Figure 3: Cross-Sectional Electric Field Profiles of a (a) standalone microstripline, and (b) standalone meandered SSPP Interconnects at $4$GHz
  • Figure 4: (a) Geometric features of two adjacent Microstriplines (b) Geometric features of two adjacent meandered SSPP Interconnects (c) Cross-sectional geometry of interconnect with intermediate oxide layer on silicon substrate
  • Figure 5: Attenuation characteristics of single channel interconnect for different substrate structures (a) Microstripline (b) meandered SSPP Interconnect
  • ...and 3 more figures