Readout of Microwave Kinetic Inductance Detector (MKID) Arrays for Habitable Worlds Observatory Using a Polyphase Filterbank Algorithm

TL;DR

The paper tackles scalable, high-resolution readout of large MKID arrays for the Habitable Worlds Observatory by developing a space-qualified FPGA implementation of a polyphase filter bank (PFB) based two-stage channelization. It adopts a critically sampled CS PFB in a staged design and plans to transition to a WOLA PFB to achieve higher spectral isolation within the mission's bandwidth and tone-precision requirements, targeting $F_s=5$ GHz and $Delta f = 10$ kHz across a $2.4$ GHz science band. The authors validate the approach through a fixed-point design methodology (frequency planning, fixed-point modeling, hardware implementation) and hardware testing on Space-grade platforms, demonstrating reduced spectral leakage compared with direct FFT channelizers. This work provides a practical, resource-efficient path toward scalable, high-density MKID readouts for space missions, with a clear TRL progression to spaceflight-grade VHDL implementations.

Abstract

The Habitable Worlds Observatory (HWO), a nextgeneration ultraviolet/optical/infrared space telescope, will require detector technologies capable of supporting substantially larger pixel-count arrays than those flown on previous missions. Microwave Kinetic Inductance Detectors (MKIDs) provide a scalable solution through microwave multiplexing and have already been demonstrated in balloon-borne instruments using Field-Programmable Gate Arrays (FPGAs) for real-time signal processing. A central element of MKID readout is the Polyphase Filter Bank (PFB) spectrometer, which converts digitized timedomain signals into finely resolved frequency channels for subsequent analysis. To meet the demands for broader bandwidths and higher spectral resolution driven by emerging science goals, efficient FPGA-based implementations of the PFB are essential. This work presents current results from a fixed-point digital design methodology for deploying the PFB architecture on spacequalified FPGAs. The approach emphasizes efficient resource utilization and numerical precision while satisfying stringent performance constraints, enabling scalable, high-resolution spectral processing for future space observatories and remote sensing applications.

Figures (11)

• Figure 1: The proposed readout system builds upon high-TRL modular SpaceCube hardware. Left: SpaceCube v3.0 Mini FPGA card (primary side pictured) with a Xilinx Kintex KU060. Right: full SpaceCube electronics system with 1U CubeSat cards inserted into a backplane. casper_toolflow, jamisonhooks2025developmentspacequalifiedsignal
• Figure 2: A two-stage frequency translation algorithm (coarse and fine channelization) is used to efficiently achieve the required 10 kHz spectral resolution for MKID readout. casper_toolflow, jamisonhooks2025developmentspacequalifiedsignal
• Figure 3: Comparison of the single-bin frequency response between a Polyphase Filter Bank (PFB) and a direct FFT. The PFB shows significantly reduced spectral leakage and lower sidelobe levels compared to the FFT, resulting in improved channel separation due to the filtering effect of the polyphase window. A zoomed-in view highlights these differences clearly down to a noise floor of –50 dB.
• Figure 4: Block diagram of the Critically-Sampled Polyphase Filter Bank (PFB) architecture. The input signal is segmented and filtered using polyphase components of a prototype filter, followed by an $N$-point FFT. This configuration provides contiguous, non-overlapping spectral bins with maximum efficiency and minimal FPGA resource usage.
• Figure 5: Block diagram of the Weighted Overlap-Add (WOLA) Polyphase Filter Bank architecture. The input signal is processed in overlapping $M/2$ segments before filtering with polyphase components. A circular buffer applies phase correction prior to streaming data into an $N$-point FFT. This overlap and weighting significantly reduce spectral leakage and enhance channel isolation, at the expense of increased FPGA resource usage.