$ρ$Hammer: Reviving RowHammer Attacks on New Architectures via Prefetching

TL;DR

This work revisits Rowhammer viability on modern Intel architectures and shows that load-based hammering is insufficient on Alder Lake and Raptor Lake. It introduces ρHammer, a framework combining fast DRAM address-mapping reverse-engineering, prefetch-based hammering with bank-level parallelism, and a counter-speculation technique to stabilize prefetch order, achieving dramatically higher flip counts and rates. The evaluation demonstrates up to 200K+ additional bit flips in 2 hours, 112× improvements over baselines on Comet/Rocket Lake, and reliable exploitation on Alder/Raptor Lake where prior methods fail, while also enabling end-to-end PTE corruption. These findings underscore the need for stronger mitigations (e.g., BIOS pTRR and future DDR5 defenses) and motivate ongoing research into robust memory-protection mechanisms.

Abstract

Rowhammer is a critical vulnerability in dynamic random access memory (DRAM) that continues to pose a significant threat to various systems. However, we find that conventional load-based attacks are becoming highly ineffective on the most recent architectures such as Intel Alder and Raptor Lake. In this paper, we present $ρ$Hammer, a new Rowhammer framework that systematically overcomes three core challenges impeding attacks on these new architectures. First, we design an efficient and generic DRAM address mapping reverse-engineering method that uses selective pairwise measurements and structured deduction, enabling recovery of complex mappings within seconds on the latest memory controllers. Second, to break through the activation rate bottleneck of load-based hammering, we introduce a novel prefetch-based hammering paradigm that leverages the asynchronous nature of x86 prefetch instructions and is further enhanced by multi-bank parallelism to maximize throughput. Third, recognizing that speculative execution causes more severe disorder issues for prefetching, which cannot be simply mitigated by memory barriers, we develop a counter-speculation hammering technique using control-flow obfuscation and optimized NOP-based pseudo-barriers to maintain prefetch order with minimal overhead. Evaluations across four latest Intel architectures demonstrate $ρ$Hammer's breakthrough effectiveness: it induces up to 200K+ additional bit flips within 2-hour attack pattern fuzzing processes and has a 112x higher flip rate than the load-based hammering baselines on Comet and Rocket Lake. Also, we are the first to revive Rowhammer attacks on the latest Raptor Lake architecture, where baselines completely fail, achieving stable flip rates of 2,291/min and fast end-to-end exploitation.

Figures (11)

• Figure 1: DRAM hierarchical organization.
• Figure 2: A traditional DRAM address mapping example.
• Figure 3: Top-down density distribution map of access latencies with an example threshold; the color scale indicates the proportion of address pairs.
• Figure 4: Heatmap of $T_{SBDR}(M, \{b_x,b_y\})$ in ns on Comet Lake (left) and Raptor Lake (right), representing traditional and recent mappings, respectively.
• Figure 5: Overview of $\rho$Hammer's workflow. B/R refers to bank/row.