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Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project

Giovanni Agosta, Stefano Cherubin, Derek Christ, Francesco Conti, Asbjørn Djupdal, Matthias Jung, Georgios Keramidas, Roberto Passerone, Paolo Rech, Elisa Ricci, Philippe Velha, Flavio Vella, Kasim Sinan Yildirim, Nils Wilbert

TL;DR

ARCHYTAS tackles the energy, efficiency, and scalability bottlenecks of AI on edge defense platforms by exploring post-CMOS accelerators (optoelectronic, PIM/NVM, and neuromorphic) and by building a cohesive HW/SW co-design with a full-stack simulation and a compiler/toolchain. The project proposes a Scalable Compute Fabric based on a NoC that can integrate heterogeneous units, a DRAMSys-based PIM/NVM system-level simulator, and a TAFFO/MLIR-backed precision-tuning compiler to map neural workloads to diverse accelerators. Key contributions include a unified simulation and benchmarking framework, PIM/NVM-aware system models, and algorithm- and architecture-aware optimizations such as pruning, sparsification, and dynamic quantization integrated into the compiler stack. The work aims to enable energy-efficient, high-throughput AI for defense applications, leveraging chiplet integration, high-bandwidth memories, and programmable heterogeneity to improve performance-per-watt on constrained platforms.

Abstract

ARCHYTAS aims to design and evaluate non-conventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project

TL;DR

ARCHYTAS tackles the energy, efficiency, and scalability bottlenecks of AI on edge defense platforms by exploring post-CMOS accelerators (optoelectronic, PIM/NVM, and neuromorphic) and by building a cohesive HW/SW co-design with a full-stack simulation and a compiler/toolchain. The project proposes a Scalable Compute Fabric based on a NoC that can integrate heterogeneous units, a DRAMSys-based PIM/NVM system-level simulator, and a TAFFO/MLIR-backed precision-tuning compiler to map neural workloads to diverse accelerators. Key contributions include a unified simulation and benchmarking framework, PIM/NVM-aware system models, and algorithm- and architecture-aware optimizations such as pruning, sparsification, and dynamic quantization integrated into the compiler stack. The work aims to enable energy-efficient, high-throughput AI for defense applications, leveraging chiplet integration, high-bandwidth memories, and programmable heterogeneity to improve performance-per-watt on constrained platforms.

Abstract

ARCHYTAS aims to design and evaluate non-conventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.
Paper Structure (10 sections, 2 figures)

This paper contains 10 sections, 2 figures.

Table of Contents

  1. Introduction
  2. The ARCHYTAS Consortium
  3. Post-CMOS Acceleration
  4. System Architecture for Accelerator Integration
  5. Simulation of Processing-In-Memory with DRAMSYS
  6. Compiler Support for Neural Network Mapping
  7. Compilers for optimized code generation
  8. Pruning and sparsification for digital and analogue devices
  9. Precision tuning approach
  10. Conclusions

Figures (2)

  • Figure 1: ARCHYTAS Scalable Compute Fabric (left) with three supported Compute Unit (CU) templates: A. stand-alone accelerator with NoC interface; B. accelerator integrated within a light-weight wrapper with RISC-V controller, local tightly-coupled data memory, and DMA; C. accelerator(s) integrated in a multi-core RISC-V cluster based on the PULP platform paradigm.
  • Figure 2: ARCHYTAS Compiler Toolchain: orange boxes represent external dialects, yellow box represent custom dialects capturing the specific aspects of PIM devices