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Implémentation Efficiente de Fonctions de Convolution sur FPGA à l'Aide de Blocs Paramétrables et d'Approximations Polynomiales

Philippe Magalhães, Virginie Fresse, Benoît Suffran, Olivier Alata

TL;DR

This study tackles the challenge of deploying CNNs on FPGAs under tight resource constraints and long design cycles. It introduces a library of four configurable convolution blocks implemented in fixed-point hardware and a data-driven framework that builds polynomial models to predict FPGA resource usage from block configurations, validated on a ZCU104 platform with 196 synthesis configurations. The resulting models achieve high accuracy (e.g., $R^2$ values near 1 for several blocks) and enable resource-aware block allocation that can utilize up to ~80% of FPGA capacity, thus accelerating design-space exploration and aiding platform selection. The work offers a practical path toward rapid, hardware-aware CNN deployment and can be extended to additional CNN layers and metrics such as energy or latency.

Abstract

Implementing convolutional neural networks (CNNs) on field-programmable gate arrays (FPGAs) has emerged as a promising alternative to GPUs, offering lower latency, greater power efficiency and greater flexibility. However, this development remains complex due to the hardware knowledge required and the long synthesis, placement and routing stages, which slow down design cycles and prevent rapid exploration of network configurations, making resource optimisation under severe constraints particularly challenging. This paper proposes a library of configurable convolution Blocks designed to optimize FPGA implementation and adapt to available resources. It also presents a methodological framework for developing mathematical models that predict FPGA resources utilization. The approach is validated by analyzing the correlation between the parameters, followed by error metrics. The results show that the designed blocks enable adaptation of convolution layers to hardware constraints, and that the models accurately predict resource consumption, providing a useful tool for FPGA selection and optimized CNN deployment.

Implémentation Efficiente de Fonctions de Convolution sur FPGA à l'Aide de Blocs Paramétrables et d'Approximations Polynomiales

TL;DR

This study tackles the challenge of deploying CNNs on FPGAs under tight resource constraints and long design cycles. It introduces a library of four configurable convolution blocks implemented in fixed-point hardware and a data-driven framework that builds polynomial models to predict FPGA resource usage from block configurations, validated on a ZCU104 platform with 196 synthesis configurations. The resulting models achieve high accuracy (e.g., values near 1 for several blocks) and enable resource-aware block allocation that can utilize up to ~80% of FPGA capacity, thus accelerating design-space exploration and aiding platform selection. The work offers a practical path toward rapid, hardware-aware CNN deployment and can be extended to additional CNN layers and metrics such as energy or latency.

Abstract

Implementing convolutional neural networks (CNNs) on field-programmable gate arrays (FPGAs) has emerged as a promising alternative to GPUs, offering lower latency, greater power efficiency and greater flexibility. However, this development remains complex due to the hardware knowledge required and the long synthesis, placement and routing stages, which slow down design cycles and prevent rapid exploration of network configurations, making resource optimisation under severe constraints particularly challenging. This paper proposes a library of configurable convolution Blocks designed to optimize FPGA implementation and adapt to available resources. It also presents a methodological framework for developing mathematical models that predict FPGA resources utilization. The approach is validated by analyzing the correlation between the parameters, followed by error metrics. The results show that the designed blocks enable adaptation of convolution layers to hardware constraints, and that the models accurately predict resource consumption, providing a useful tool for FPGA selection and optimized CNN deployment.
Paper Structure (11 sections, 3 figures, 5 tables, 1 algorithm)

This paper contains 11 sections, 3 figures, 5 tables, 1 algorithm.

Figures (3)

  • Figure 1: Consommation de LLUT - $Conv_1$.
  • Figure 2: Consommation de LLUT - $Conv_2$.
  • Figure 3: Consommation de LLUT - $Conv_3$.