FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures

TL;DR

FVDebug presents an end-to-end, LLM-driven debugging system for formal verification failures that converts counter-examples into a structured causal graph, enabling automated root-cause analysis and RTL patch generation. The four-stage pipeline—Causal Graph Synthesis, Graph Scanner with for-and-against prompting, Insight Rover for agentic hypothesis exploration, and Fix Generator with ensemble strategies—mirrors industrial debugging workflows. Evaluations on open benchmarks and real-world industrial counterexamples show high hypothesis quality and strong fix rates, with notable performance on large, production-scale designs. The work demonstrates practical impact by reducing manual debugging time and providing platform-ready, patchable results suitable for collaboration between verification engineers and RTL designers.

Abstract

Debugging formal verification (FV) failures represents one of the most time-consuming bottlenecks in modern hardware design workflows. When properties fail, engineers must manually trace through complex counter-examples spanning multiple cycles, analyze waveforms, and cross-reference design specifications to identify root causes - a process that can consume hours or days per bug. Existing solutions are largely limited to manual waveform viewers or simple automated tools that cannot reason about the complex interplay between design intent and implementation logic. We present FVDebug, an intelligent system that automates root-cause analysis by combining multiple data sources - waveforms, RTL code, design specifications - to transform failure traces into actionable insights. Our approach features a novel pipeline: (1) Causal Graph Synthesis that structures failure traces into directed acyclic graphs, (2) Graph Scanner using batched Large Language Model (LLM) analysis with for-and-against prompting to identify suspicious nodes, and (3) Insight Rover leveraging agentic narrative exploration to generate high-level causal explanations. FVDebug further provides concrete RTL fixes through its Fix Generator. Evaluated on open benchmarks, FVDebug attains high hypothesis quality and strong Pass@k fix rates. We further report results on two proprietary, production-scale FV counterexamples. These results demonstrate FVDebug's applicability from academic benchmarks to industrial designs.

Figures (16)

• Figure 1: Overview of FVDebug. The system transforms formal verification counter-examples into actionable debugging insights through four stages: (1) Causal Graph Synthesis builds a directed acyclic graph capturing signal dependencies, (2) Graph Scanner performs efficient batched analysis to identify suspicious nodes, (3) Insight Rover explores competing hypotheses through intelligent graph navigation, and (4) Fix Generator produces concrete RTL patches and debugging reports. "C" denotes cycle in the example output of Graph Scanner.
• Figure 2: CVA6 LSU failure: textual subgraph (left) and full-graph visualization (right).
• Figure 3: Causal graph automatically generated by FVDebug for the accumulator verification failure.
• Figure 4: Graph Scanner prompt template (part 1 of 3).
• Figure 5: Graph Scanner prompt template (part 2 of 3) with JSON response schema.