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LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models

Kiran Thorat, Jiahui Zhao, Yaotian Liu, Amit Hasan, Hongwu Peng, Xi Xie, Bin Lei, Caiwen Ding

TL;DR

The paper tackles the challenge of generating Verilog code with LLMs while satisfying tight PPA constraints. It introduces VeriPPA, a two-stage framework where an initial stage ensures syntactic and functional correctness of generated Verilog, followed by a PPA-focused refinement stage that uses synthesis feedback and in-context prompts to meet timing, power, and area requirements. Key contributions include VeriRectify's multi-round error feedback, integration of ICARUS testing with testbenches, PPA-aware prompting, and a comparative cost analysis showing reduced tokens and MACs relative to SOTA approaches. Empirical results on RTLLM and VerilogEval datasets demonstrate significant gains in correctness (up to 81.37% syntactic and 62.06% functional) and successful PPA optimization for multiple designs, highlighting the framework's potential to automate hardware design workflows at scale.

Abstract

Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the field of chip design using LLMs, specifically in Power- Performance-Area (PPA) optimization and the generation of accurate Verilog codes for circuit designs. We introduce a novel framework VeriPPA designed to optimize PPA and generate Verilog code using LLMs. Our method includes a two-stage process where the first stage focuses on improving the functional and syntactic correctness of the generated Verilog codes, while the second stage focuses on optimizing the Verilog codes to meet PPA constraints of circuit designs, a crucial element of chip design. Our framework achieves an 81.37% success rate in syntactic correctness and 62.06% in functional correctness for code genera- tion, outperforming current state-of-the-art (SOTA) methods. On the RTLLM dataset. On the VerilogEval dataset, our framework achieves 99.56% syntactic correctness and 43.79% functional correctness, also surpassing SOTA, which stands at 92.11% for syntactic correctness and 33.57% for functional correctness. Furthermore, Our framework able to optimize the PPA of the designs. These results highlight the potential of LLMs in handling complex technical areas and indicate an encouraging development in the automation of chip design processes.

LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models

TL;DR

The paper tackles the challenge of generating Verilog code with LLMs while satisfying tight PPA constraints. It introduces VeriPPA, a two-stage framework where an initial stage ensures syntactic and functional correctness of generated Verilog, followed by a PPA-focused refinement stage that uses synthesis feedback and in-context prompts to meet timing, power, and area requirements. Key contributions include VeriRectify's multi-round error feedback, integration of ICARUS testing with testbenches, PPA-aware prompting, and a comparative cost analysis showing reduced tokens and MACs relative to SOTA approaches. Empirical results on RTLLM and VerilogEval datasets demonstrate significant gains in correctness (up to 81.37% syntactic and 62.06% functional) and successful PPA optimization for multiple designs, highlighting the framework's potential to automate hardware design workflows at scale.

Abstract

Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the field of chip design using LLMs, specifically in Power- Performance-Area (PPA) optimization and the generation of accurate Verilog codes for circuit designs. We introduce a novel framework VeriPPA designed to optimize PPA and generate Verilog code using LLMs. Our method includes a two-stage process where the first stage focuses on improving the functional and syntactic correctness of the generated Verilog codes, while the second stage focuses on optimizing the Verilog codes to meet PPA constraints of circuit designs, a crucial element of chip design. Our framework achieves an 81.37% success rate in syntactic correctness and 62.06% in functional correctness for code genera- tion, outperforming current state-of-the-art (SOTA) methods. On the RTLLM dataset. On the VerilogEval dataset, our framework achieves 99.56% syntactic correctness and 43.79% functional correctness, also surpassing SOTA, which stands at 92.11% for syntactic correctness and 33.57% for functional correctness. Furthermore, Our framework able to optimize the PPA of the designs. These results highlight the potential of LLMs in handling complex technical areas and indicate an encouraging development in the automation of chip design processes.
Paper Structure (14 sections, 2 equations, 3 figures, 7 tables)

This paper contains 14 sections, 2 equations, 3 figures, 7 tables.

Table of Contents

  1. Introduction
  2. Backgound and Related Work
  3. Framework
  4. Design Overview
  5. Code Generation and Testing
  6. VeriRectify
  7. Power Performance and Area (PPA).
  8. Evaluation
  9. Datasets
  10. Experimental Setup
  11. Generation Correctness
  12. PPA Optimization
  13. Computational cost analysis between self-planning (SOTA) and VeriPPA
  14. Conclusion

Figures (3)

  • Figure 1: VeriPPA framework.
  • Figure 2: (a) Multi-round conversation with error feedback; (b) Workflow of the process.
  • Figure 3: Optimization Flow; (a) Syntactically and functionally correct designs, (b) Synopsis compiler, (c) Non-optimized PPA results based on 7nm ASAP technology, (d) In-context learning to optimize PPA, (e) PPA aware prompt, (e) Optimized results