DiffPlace: A Conditional Diffusion Framework for Simultaneous VLSI Placement Beyond Sequential Paradigms

TL;DR

DiffPlace reframes chip placement as a conditional denoising diffusion problem to enable simultaneous, globally optimized module placement that generalizes across unseen netlists without retraining. By integrating an energy-guided, constraint-aware sampling strategy and a graph-neural network conditioned score model, it balances multiple objectives such as $HPWL$, congestion, and overlap while enforcing legal placements. The approach demonstrates competitive or superior results on ISPD05 and IBM benchmarks, with strong transfer learning capabilities (few-shot adaptation and cross-benchmark generalization) and notable reductions in training overhead compared to sequential RL methods. This diffusion-based framework offers a practical, scalable path toward automated high-quality VLSI placement, with potential extensions to timing-aware and full placement-and-routing co-optimization in industrial toolchains.

Abstract

Chip placement, the task of determining optimal positions of circuit modules on a chip canvas, is a critical step in the VLSI design flow that directly impacts performance, power consumption, and routability. Traditional methods rely on analytical optimization or reinforcement learning, which struggle with hard placement constraints or require expensive online training for each new circuit design. To address these limitations, we introduce DiffPlace, a framework that formulates chip placement as a conditional denoising diffusion process, enabling transferable placement policies that generalize to unseen circuit netlists without retraining. DiffPlace leverages the generative capabilities of diffusion models to efficiently explore the vast space of placement while conditioning on circuit connectivity and relative quality metrics to identify optimal solutions globally. Our approach combines energy-guided sampling with constrained manifold diffusion to ensure placement legality, achieving extremely low overlap across all experimental scenarios. Our method bridges the gap between optimization-based and learning-based approaches, offering a practical path toward automated, high-quality chip placement for modern VLSI design. Our source code is publicly available at: https://github.com/HySonLab/DiffPlace/

Figures (6)

• Figure 1: Progressive denoising process for simultaneous placement generation. The sequence illustrates iterative refinement from random Gaussian noise $x_T$ to final placement $x_0$, with intermediate predictions $\hat{x}_0$ shown at intervals. Unlike sequential RL approaches that place components one by one, our method simultaneously optimizes all module positions. Existing methods Lai2022Lee2025 focus exclusively on arranging movable components, our framework holistically addresses both fixed and movable elements within the placement space.
• Figure 2: Comparing the overall pipelines between (a) online RL placement and (b) diffusion model-based placement (ours). In (a), the online RL model continuously interacts with the environment (i.e., a placement simulator or an EDA design tool for obtaining metrics from placement designs, with time consumption proportional to circuit complexity) to learn policy from scratch. This results in substantial training time for each new circuit in standard benchmarks. In (b), our diffusion model approach allows for efficient generation of placements in a single pass, eliminating the need for iterative environment interactions during inference. When presented with an unseen circuit, our diffusion model can generalize effectively with minimal adaptation, leveraging its learned representations of circuit patterns and placement constraints. This approach significantly reduces runtime compared to previous online RL methods while maintaining or improving placement quality.
• Figure 3: Degree distribution comparison. Real circuit data averaged from 15 ISPD 2015-2019 benchmarks. Shaded region shows theoretical range $\alpha \in [1.8, 2.3]$ for digital circuits. Error bars indicate standard deviation across benchmarks.
• Figure 4: Overview of the DiffPlace denoising diffusion model for VLSI chip placement. The model takes as input a noisy placement initialized from Gaussian noise and iteratively refines it through a learned denoising process, conditioned on the circuit’s netlist graph and a relative energy score. The architecture combines graph neural network encodings of the netlist with timestep and energy embeddings to predict noise components, guiding the system toward valid, high-quality placements. This approach enables simultaneous placement of all modules, supports constraint enforcement (e.g., overlap, congestion), and generalizes efficiently to unseen circuit designs through transfer learning.
• Figure 5: Visualization of placement results on adaptec3 benchmark: (a) GraphPlace, (b) DeepPR (c) MaskPlace, and (d) Ours. DiffPlace produces more compact placements with shorter wirelength compared to existing approaches.