Limited Read-Write/Set Hardware Transactional Memory without modifying the ISA or the Coherence Protocol
Konstantinos Kafousis
TL;DR
This work presents a constrained hardware transactional memory design that delivers multi-word atomicity without adding ISA or coherence protocol changes. The approach extends the semantics of load-linked and store-conditional instructions and confines all transactional logic to the L1 data cache using a small set of Transaction Status Holding Registers. It adopts lazy version management and eager conflict detection, plus two hardware-only forward-progress mechanisms to guarantee progress under contention. The design is evaluated in gem5 SE mode across microbenchmarks and data-structure benchmarks, demonstrating that read/write-sets of about eight cache lines suffice and that performance is strong when contention is spread across multiple nodes. Overall, the paper argues that practical HTM can be achieved with limited hardware changes and preserved interoperability, enabling lock-free programming for a useful class of multi-word atomic operations.
Abstract
Hardware Transactional Memory (HTM) allows lock-free programming as easy as with traditional coarse-grain locks or similar, while benefiting from the performance advantages of fine-grained locking. Many HTM implementations have been proposed, but they have not received widespread adoption because of their high hardware complexity, their need for additions to the Instruction Set Architecture (ISA), and often for modifications to the cache coherence protocol. We show that HTM can be implemented without adding new instructions -- merely by extending the semantics of two existing, Load-Linked and Store-Conditional. Also, our proposed design does not modify or extend standard coherence protocols. We further propose to drastically simplify the implementation of HTM -- confined to modifications in the L1 Data Cache only -- by restricting it to applications where the write set plus the read set of each transaction do not exceed a small number of cache lines. We also propose two alternative mechanisms to guarantee forward progress, both based on detecting retrial attempts. We simulated our proposed design in Gem5, and we used it to implement several popular concurrent data structures, showing that a maximum of eight (8) words (cache lines) suffice for the write plus read sets. We provide a detailed explanation of selected implementations, clarifying the intended usage of our HTM from a programmer's perspective. We evaluated our HTM under varying contention levels to explore its scalability limits. The results indicate that our HTM provides good performance in concurrent data structures when contention is spread across multiple nodes: in such cases, the percentage of aborts relative to successful commits is very low. In the atomic fetch-and-increment benchmark for multiple shared counters, the results show that, under low-congestion, our HTM improves performance relative to the TTS lock.