Fast and Compact Tsetlin Machine Inference on CPUs Using Instruction-Level Optimization

TL;DR

The paper tackles the challenge of fast TM inference on CPUs for edge devices by introducing a bitwise, instruction-level inference design that packs literals and Tsetlin Automata actions into $m = \lceil \frac{2n}{32} \rceil$ 32-bit words and evaluates clauses via AND operations, enabling an early exit when a word is not all ones. It further proposes a post-training, pre-inference Reorder strategy based on the metrics $P(L_{ijk})$ and $P(include_{ijk})$ to maximize early exits and Booleanization to map features to literals $L_{ijk}$. Experimental results on gem5-ARM simulations using Iris and MNIST show substantial latency reductions, with bitwise+early-exit achieving up to 94%+ improvements, and the Reorder extension providing additional gains up to 96.71% while preserving code density. Overall, the approach enables real-time, low-power TM inference on resource-constrained CPUs, offering a compact model representation and high interpretability inherent to TM.

Abstract

The Tsetlin Machine (TM) offers high-speed inference on resource-constrained devices such as CPUs. Its logic-driven operations naturally lend themselves to parallel execution on modern CPU architectures. Motivated by this, we propose an efficient software implementation of the TM by leveraging instruction-level bitwise operations for compact model representation and accelerated processing. To further improve inference speed, we introduce an early exit mechanism, which exploits the TM's AND-based clause evaluation to avoid unnecessary computations. Building upon this, we propose a literal Reorder strategy designed to maximize the likelihood of early exits. This strategy is applied during a post-training, pre-inference stage through statistical analysis of all literals and the corresponding actions of their associated Tsetlin Automata (TA), introducing negligible runtime overhead. Experimental results using the gem5 simulator with an ARM processor show that our optimized implementation reduces inference time by up to 96.71% compared to the conventional integer-based TM implementations while maintaining comparable code density.

Figures (4)

• Figure 1: TM inference clause output
• Figure 2: Integer operation inference
• Figure 3: Bitwise operation with early exit
• Figure 4: Booleanization with Reorder index