A Tsetlin Machine Image Classification Accelerator on a Flexible Substrate

TL;DR

This work demonstrates the first digital Tsetlin Machine implementations on a flexible IGZO-based FlexIC substrate, addressing the rigidity of silicon chips for edge AI. By training TM instances with fixed hyperparameters and translating the results into RTL, the authors realize two TM inference engines on flexible footprints: a full-scale design with about 6800 NAND2-equivalent gates achieving 98.5% accuracy on an 8x8 handwritten-digit task, and a compact design with about 1420 gates achieving 93%. The four-stage pipeline enables 3-clock-cycle latency, with successful RTL and post-layout verification on two die sizes, and a detailed PPA analysis showing favorable power-area-performance trade-offs. These results validate the practicality of flexible, interpretable ML accelerators for wearable healthcare and edge sensing applications.

Abstract

This paper introduces the first implementation of digital Tsetlin Machines (TMs) on flexible integrated circuit (FlexIC) using Pragmatic's 600nm IGZO-based FlexIC technology. TMs, known for their energy efficiency, interpretability, and suitability for edge computing, have previously been limited by the rigidity of conventional silicon-based chips. We develop two TM inference models as FlexICs: one achieving 98.5% accuracy using 6800 NAND2 equivalent logic gates with an area of 8X8 mm2, and a second more compact version achieving slightly lower prediction accuracy of 93% but using only 1420 NAND2 equivalent gates with an area of 4X4 mm2, both of which are custom-designed for an 8X8-pixel handwritten digit recognition dataset. The paper demonstrates the feasibility of deploying flexible TM inference engines into wearable healthcare and edge computing applications.

Figures (9)

• Figure 1: Hardware microarchitecture of the two TM inference models
• Figure 2: Layouts of the compact and full-scale TM FlexICs
• Figure 3: RTL simulation of the compact design
• Figure 4: Parasitic simulation of the compact design
• Figure 5: Worst timing slack figures.