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Obvious and non-obvious aspects of digital Self-Excited-Loops for SRF cavity control

Larry Doolittle, Shreeharshini Murthy, Matei Guran, Lennon Reyes, Shrividhyaa Sankar Raman, Philip Varghese

TL;DR

The paper analyzes Self-Excited Loops (SEL) for narrow-band SRF cavity control, focusing on Delayen's approach to achieve early amplitude stability and subsequent phase/tuning loop closure. It compares traditional analog SEL behavior with modern digital implementations based on CORDIC, detailing how latency, stability, and resiliency are affected across multiple hardware topologies (e.g., LBNL, JLab, S-DALINAC, BARC, GDR) and highlighting the role of a Stateful Phase Resolver for off-frequency operation. Key contributions include a structured overview of PI-based stabilization, CORDIC-based processing, and a survey of digital SEL topologies, with practical guidance on latency-reduction strategies. The work informs robust, low-latency FPGA-based LLRF control of SRF cavities, enabling stable operation under detuning and microphonics and providing a roadmap for cross-lab code sharing and topology choice.

Abstract

In 1978, Delayen showed how Self-Excited Loops (SEL) can be used to great advantage for controlling narrow-band SRF cavities. Its key capability is establishing closed-loop amplitude control early in the setup process, stabilizing Lorentz forces to allow cavity tuning and phase loop setup in a stable environment. As people around the world implement this basic idea with modern FPGA DSP technology, multiple variations and operational scenarios creep in that have both obvious and non-obvious ramifications for latency, feedback stability, and resiliency. This paper will review the key properties of a Delayen-style SEL when set up for open-loop, amplitude stabilized, and phase-stabilized modes. Then the original analog circuit will be compared and contrasted with the known variations of digital CORDIC-based implementations.

Obvious and non-obvious aspects of digital Self-Excited-Loops for SRF cavity control

TL;DR

The paper analyzes Self-Excited Loops (SEL) for narrow-band SRF cavity control, focusing on Delayen's approach to achieve early amplitude stability and subsequent phase/tuning loop closure. It compares traditional analog SEL behavior with modern digital implementations based on CORDIC, detailing how latency, stability, and resiliency are affected across multiple hardware topologies (e.g., LBNL, JLab, S-DALINAC, BARC, GDR) and highlighting the role of a Stateful Phase Resolver for off-frequency operation. Key contributions include a structured overview of PI-based stabilization, CORDIC-based processing, and a survey of digital SEL topologies, with practical guidance on latency-reduction strategies. The work informs robust, low-latency FPGA-based LLRF control of SRF cavities, enabling stable operation under detuning and microphonics and providing a roadmap for cross-lab code sharing and topology choice.

Abstract

In 1978, Delayen showed how Self-Excited Loops (SEL) can be used to great advantage for controlling narrow-band SRF cavities. Its key capability is establishing closed-loop amplitude control early in the setup process, stabilizing Lorentz forces to allow cavity tuning and phase loop setup in a stable environment. As people around the world implement this basic idea with modern FPGA DSP technology, multiple variations and operational scenarios creep in that have both obvious and non-obvious ramifications for latency, feedback stability, and resiliency. This paper will review the key properties of a Delayen-style SEL when set up for open-loop, amplitude stabilized, and phase-stabilized modes. Then the original analog circuit will be compared and contrasted with the known variations of digital CORDIC-based implementations.
Paper Structure (10 sections, 7 equations, 16 figures)

This paper contains 10 sections, 7 equations, 16 figures.

Figures (16)

  • Figure 1: Textbook SEL oscillator
  • Figure 2: Delayen 1978 cavity controller
  • Figure 3: CORDIC internal structure
  • Figure 4: CORDIC use cases
  • Figure 5: PI controller structure and representation
  • ...and 11 more figures