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ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems

İsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostancı, Haocong Luo, A. Giray Yağlıkçı, Onur Mutlu

TL;DR

This work uncovers ColumnDisturb, a previously uncharacterized column-based read disturbance in real DRAM chips, where hammering or pressing an aggressor row perturbs cells along the same bitlines across up to three subarrays, causing thousands of bitflips. Through extensive experiments on 216 DDR4 and 4 HBM2 chips, the authors show ColumnDisturb is widespread, worsens with technology scaling, and can occur within standard refresh windows, unlike traditional retention-only failures. They analyze how temperature, aggressor timing, data patterns, and ECC interact with ColumnDisturb, demonstrating that conventional ECC cannot fully mitigate it and that retention-aware refresh strategies (like RAIDR) lose much of their benefits in its presence. The paper proposes mitigation approaches, including Proactively Refreshing ColumnDisturb Victim Rows (PRVR), and highlights the need for future research to develop resilient, column-aware DRAM refresh mechanisms to preserve system performance and reliability. Overall, ColumnDisturb represents a fundamental shift in understanding DRAM read disturbance and has significant implications for the design of robust, future memory systems.

Abstract

We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) open, we show that it is possible to disturb DRAM cells through a DRAM column (i.e., bitline) and induce bitflips in DRAM cells sharing the same columns as the aggressor row (across multiple DRAM subarrays). With ColumnDisturb, the activation of a single row concurrently disturbs cells across as many as three subarrays (e.g., 3072 rows) as opposed to RowHammer/RowPress, which affect only a few neighboring rows of the aggressor row in a single subarray. We rigorously characterize ColumnDisturb and its characteristics under various operational conditions using 216 DDR4 and 4 HBM2 chips from three major manufacturers. Among our 27 key experimental observations, we highlight two major results and their implications. First, ColumnDisturb affects chips from all three major manufacturers and worsens as DRAM technology scales down to smaller node sizes (e.g., the minimum time to induce the first ColumnDisturb bitflip reduces by up to 5.06x). We observe that, in existing DRAM chips, ColumnDisturb induces bitflips within a standard DDR4 refresh window (e.g., in 63.6 ms) in multiple cells. We predict that, as DRAM technology node size reduces, ColumnDisturb would worsen in future DRAM chips, likely causing many more bitflips in the standard refresh window. Second, ColumnDisturb induces bitflips in many (up to 198x) more rows than retention failures. Therefore, ColumnDisturb has strong implications for retention-aware refresh mechanisms that leverage the heterogeneity in cell retention times: our detailed analyses show that ColumnDisturb greatly reduces the benefits of such mechanisms.

ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems

TL;DR

This work uncovers ColumnDisturb, a previously uncharacterized column-based read disturbance in real DRAM chips, where hammering or pressing an aggressor row perturbs cells along the same bitlines across up to three subarrays, causing thousands of bitflips. Through extensive experiments on 216 DDR4 and 4 HBM2 chips, the authors show ColumnDisturb is widespread, worsens with technology scaling, and can occur within standard refresh windows, unlike traditional retention-only failures. They analyze how temperature, aggressor timing, data patterns, and ECC interact with ColumnDisturb, demonstrating that conventional ECC cannot fully mitigate it and that retention-aware refresh strategies (like RAIDR) lose much of their benefits in its presence. The paper proposes mitigation approaches, including Proactively Refreshing ColumnDisturb Victim Rows (PRVR), and highlights the need for future research to develop resilient, column-aware DRAM refresh mechanisms to preserve system performance and reliability. Overall, ColumnDisturb represents a fundamental shift in understanding DRAM read disturbance and has significant implications for the design of robust, future memory systems.

Abstract

We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) open, we show that it is possible to disturb DRAM cells through a DRAM column (i.e., bitline) and induce bitflips in DRAM cells sharing the same columns as the aggressor row (across multiple DRAM subarrays). With ColumnDisturb, the activation of a single row concurrently disturbs cells across as many as three subarrays (e.g., 3072 rows) as opposed to RowHammer/RowPress, which affect only a few neighboring rows of the aggressor row in a single subarray. We rigorously characterize ColumnDisturb and its characteristics under various operational conditions using 216 DDR4 and 4 HBM2 chips from three major manufacturers. Among our 27 key experimental observations, we highlight two major results and their implications. First, ColumnDisturb affects chips from all three major manufacturers and worsens as DRAM technology scales down to smaller node sizes (e.g., the minimum time to induce the first ColumnDisturb bitflip reduces by up to 5.06x). We observe that, in existing DRAM chips, ColumnDisturb induces bitflips within a standard DDR4 refresh window (e.g., in 63.6 ms) in multiple cells. We predict that, as DRAM technology node size reduces, ColumnDisturb would worsen in future DRAM chips, likely causing many more bitflips in the standard refresh window. Second, ColumnDisturb induces bitflips in many (up to 198x) more rows than retention failures. Therefore, ColumnDisturb has strong implications for retention-aware refresh mechanisms that leverage the heterogeneity in cell retention times: our detailed analyses show that ColumnDisturb greatly reduces the benefits of such mechanisms.
Paper Structure (29 sections, 23 figures, 1 table)

This paper contains 29 sections, 23 figures, 1 table.

Table of Contents

  1. Introduction
  2. Background & Fundamentals
  3. Dynamic Random Access Memory (DRAM)
  4. DRAM Read Disturbance
  5. DRAM Refresh and Retention Failures
  6. Evaluation Infrastructure & Methodology
  7. COTS DRAM Testing Infrastructure
  8. Experimental Methodology
  9. Foundational Results
  10. Prevalence & Scaling Characteristics
  11. Disturbing DRAM Columns
  12. Bitflip Direction
  13. Data Pattern in Aggressor Row
  14. Aggressor Row on Time
  15. Average Voltage Level on Perturbed Columns
  16. ...and 14 more sections

Figures (23)

  • Figure 1: (a) Modern DRAM array architecture, (b) RowHammer & RowPress induce bitflips in a few neighboring rows of the aggressor row, where rows are the victims,(c) ColumnDisturb, a column-based read disturbance phenomenon that affects many rows in multiple subarrays, where columns are victims.
  • Figure 2: Number of ColumnDisturb, RowHammer, RowPress, and retention failure bitflips in three subarrays.
  • Figure 3: Organization of modern DRAM-based main memory.
  • Figure 4: Our DRAM Bender olgun2023dram based experimental setup.
  • Figure 5: Our laboratory for real DRAM chip experiments.
  • ...and 18 more figures