ScalePool: Hybrid XLink-CXL Fabric for Composable Resource Disaggregation in Unified Scale-up Domains

TL;DR

ScalePool addresses the inefficiency of existing scale-up and scale-out interconnects for large AI workloads that require both fast accelerator communication and scalable memory sharing. It proposes a hybrid fabric that uses XLink for intra-cluster accelerator communication and a hierarchical CXL-based fabric for inter-cluster coherent memory pooling, with explicit memory tiering. Key contributions include the accelerator-centric cluster architecture, the two-tier memory hierarchy (tier-1 with accelerator-local memory plus coherence-centric CXL/XLink and tier-2 disaggregated memory pool), and interface abstraction via CXL to enable heterogeneous clusters. Evaluation shows average speedups of $1.22\times$ and up to $1.84\times$ for LLM training over RDMA-based setups, and up to $4.5\times$ latency reduction for memory-intensive workloads with tier-2 memory.

Abstract

This paper proposes ScalePool, a novel cluster architecture designed to interconnect numerous accelerators using unified hardware interconnects rather than traditional long-distance networking. ScalePool integrates Accelerator-Centric Links (XLink) and Compute Express Link (CXL) into a unified XLink-CXL hybrid fabric. Specifically, ScalePool employs XLink for intra-cluster, low-latency accelerator communication, while using hierarchical CXL-based switching fabrics for scalable and coherent inter-cluster memory sharing. By abstracting interfaces through CXL, ScalePool structurally resolves interoperability constraints, enabling heterogeneous cluster operation and composable resource disaggregation. In addition, ScalePool introduces explicit memory tiering: the latency-critical tier-1 combines accelerator-local memory with coherence-centric CXL and XLink, whereas the highcapacity tier-2 employs dedicated memory nodes interconnected by a CXL-based fabric, achieving scalable and efficient memory pooling. Evaluation results show that ScalePool accelerates LLM training by 1.22x on average and up to 1.84x compared to conventional RDMA-based environments. Furthermore, the proposed tier-2 memory disaggregation strategy reduces latency by up to 4.5x for memory-intensive workloads.

Figures (5)

• Figure 1: Architectural differences.
• Figure 2: XLink-CXL hybrid fabric.
• Figure 3: Accelerator clusters.
• Figure 4: ScalePool architecture.
• Figure 5: Tiered memory architectures.