Design and simulation of a 4H-SiC low gain avalanche diode with trench-isolation

TL;DR

This study addresses the need for high-voltage, fast-timing detectors in the SiC platform by designing a 30 µm thick 4H-SiC LGAD with a $2.4\mu\mathrm{m}$ epitaxial gain layer, enabling full depletion below $500\mathrm{V}$ and internal gain up to $1\mathrm{kV}$. Edge termination is realized through trench isolation combined with deep $p^+$ JTE implants, whose dimensions are optimized via TCAD to suppress fringe-field–driven breakdown, yielding simulated breakdown voltages above $2.4\mathrm{kV}$. The simulations employ a quasi-1D geometry for I-V, C-V, and gain assessments, plus 2D breakdown studies near guard structures, guided by manufacturer tolerances. A corresponding wafer run is in process at IMB-CNM, indicating practical viability of the approach for high-voltage 4H-SiC detectors with fast timing and low dark current. Overall, the work demonstrates a viable pathway to robust, high-voltage 4H-SiC LGADs for advanced high-energy physics instrumentation.

Abstract

We present the design and simulation of a 30 $\mathrm{μm}$ thick 4H-SiC Low Gain Avalanche Diode (LGAD) optimized for high-voltage operation. A 2.4 $\mathrm{μm}$ thick epitaxially grown gain layer enables controlled internal amplification up to 1 kV reverse bias, while maintaining full depletion below 500 V. Electrical characteristics, including I-V, C-V, and gain behavior, were simulated in Synopsys Sentaurus Technology Computer-Aided Design (TCAD) using a quasi-1D geometry and verified across process-related variations in gain layer parameters. To ensure high-voltage stability and proper edge termination, a guard structure combining deep etched trenches and deep $p^+$ junction termination extension (JTE) implants was designed. TCAD simulations varying the guard structure dimensions yielded an optimized design with a breakdown voltage above 2.4 kV. A corresponding wafer run is currently processed at IMB-CNM, Barcelona.

Figures (4)

• Figure 1: Cross-section of the epitaxial structure of the 4H-SiC LGAD design (not true to scale). The edge of the front contact and the subsequent guard structure are shown. The latter consists of an etched trench and a JTE implant to further distribute fringe fields.
• Figure 2: Simulated I-V and $\mathrm{C^{-2}}$-V characteristics of a 4H-SiC LGAD without guarding structures compared to a $30µ m$ thick PIN diode.
• Figure 3: Simulated gain of a 4H-SiC LGAD without guarding structures, as a function of the applied reverse bias. Values are determined by comparing the respective integrated current pulse generated by a MIP in the LGAD structure to that of a $30µm$ PIN diode at $500V$ bias.
• Figure 4: Breakdown voltage of the SiC LGAD design versus trench width and depth for a fixed $p+$-JTE implant with a width and depth of $30µm \times 4µ m$.