Cryogenic temperature dependence and hysteresis of surface-trap-induced gate leakage in GaN high-electron-mobility transistors

TL;DR

The study probes surface-trap–induced gate leakage in GaN HEMTs from room temperature to $1.5\ \mathrm{K}$, uncovering three leakage pathways: 2D-VRH near zero gate bias, Schottky thermionic emission (TE) at positive bias, and trap-assisted leakage via Poole–Frenkel emission and trap-assisted tunneling (PFE/TAT) at negative bias, with a frozen-trap transition around $220\ \mathrm{K}$. By analyzing upward and downward gate sweeps, it identifies a trap barrier height of about $\phi_{\mathrm{PFE}}\approx 0.65$ V (upward) and $\approx 0.58$ V (downward), and shows TAT dominating below $120\ \mathrm{K}$, consistent with a frozen-trap picture. A striking opposite hysteresis of the leakage current is observed above and below $220\ \mathrm{K}$, explained by the different emission processes and trap-occupancy dynamics, and it serves as a practical diagnostic for surface-trap–related leakage. The results highlight the importance of passivation and gate-stack engineering for reliable cryogenic GaN HEMT operation and motivate further study of surface-trap physics in these devices.

Abstract

This work provides a detailed mapping of various mechanisms of surface-trap-induced gate leakage in GaN HEMTs across a temperature range from room to cryogenic levels. Two-dimensional variable-range hopping is observed at small gate bias. Under higher reverse gate bias, the leakage is dominated by the Poole--Frenkel emission above 220 K, but gradually transitions to the trap-assisted tunneling below 220 K owing to the frozen-trap effect. The trap barrier height extracted from the gate leakage current under the upward gate sweep is 0.65 V, which is 12\% higher than that from the downward sweep. The gate leakage current as a function of the gate bias exhibits clockwise hysteresis loops above 220 K but counterclockwise ones below 220 K. This remarkable opposite hysteresis phenomenon is thoroughly explained by the trap mechanisms.

Figures (5)

• Figure 1: Schematic drawing (not to scale) of the GaN HEMT.
• Figure 2: (a) $V_\mathrm{G}$ dependence at $T=300$ K and (b) temperature dependence at $V_\mathrm{G}=-1$ V of $I_\mathrm{D}$ vs. $V_\mathrm{D}$. Curves below 180 K are taken at 140, 100, 60, and 1.5 K, respectively. (c) Temperature dependence of $I_\mathrm{D}$ vs. $V_\mathrm{G}$ from 300 to 1.5 K (in steps of 25 K above 200 K, and in steps of 20 K below 200 K) at $V_\mathrm{D} = 0.1$ V. Inset: $I_\mathrm{D}$ vs. $V_\mathrm{G}$ at 300 K in the linear scale, and the corresponding transconductance $g_\mathrm{m}$. The dotted line is the linear extrapolation to extract $V_\mathrm{th}$. (d) Mobility $\mu$ (triangles) and sheet electron density $n$ (hollow circles) of the ungated device as functions of temperature. (e) $V_\text{th}$ (extracted at $I_\mathrm{D}$ = 20 $\upmu$A/mm, the dashed line shown in (c)) as a function of temperature.
• Figure 3: (a) $I_\mathrm{G}$ vs. $V_\mathrm{G}$ from room to cryogenic temperatures in steps of 20 K. (The 300-K curve is specifically shaded in a darker red to distinguish the hysteresis loop.) The solid curves represent gate voltage sweeps from negative to positive $V_\mathrm{G}$, and the dashed ones represent positive to negative $V_\mathrm{G}$ sweeps. Insets: same data in the linear scale. (b) Enlarged view of (a) for upward gate sweeps from $V_\mathrm{G}=-1$ V to $1$ V. Dashed lines are fits of the Schottky TE model. (c) Fits of the 2D-VRH model (Eq. \ref{['eq:2DVRH']}) to $\ln(|I_\mathrm{G}|)$ vs. $T^{-1/3}$ at small $V_\mathrm{G}$'s $0.3$ V, $-0.4$ V, $-1$ V, and $-2$ V, respectively. $I_\mathrm{G}$ for $T<160$ K is too small with high noise-to-signal ratios and thus cannot be fitted.
• Figure 4: Gate leakage under higher negative $V_\mathrm{G}$ ($\lesssim-4$ V) for upward gate sweeps. (a) $\ln(I_\mathrm{G}/V_\mathrm{G})$ vs. $\sqrt{|V_\mathrm{G}|}$ from room temperature to 1.5 K in steps of 10 K. Dashed lines are fits of the PFE model (Eq. \ref{['eq:PFE']}). Parameters $b(T)$ from the fits are further plotted in (b) to obtain $\phi_\mathrm{PFE}$. (c) $\ln(|I_\mathrm{G}|)$ vs. $1/|V_\mathrm{G}|$ for 210--1.5 K. The dashed line is the fit using the TAT model (Eq. \ref{['eq:TAT']}).
• Figure 5: (a) $I_\mathrm{G}$ vs. $V_\mathrm{G}$ for both upward and downward gate sweeps. Data points are taken at a step size of $\pm0.05$ V per 250, 70, and 18 ms, respectively. $I_\mathrm{G}$ normalized to its initial quantity is plotted against stress time $t$ (b) under $V_\mathrm{G}=-10$ V at different temperatures and (c) at 300 K under different $V_\mathrm{G}$'s from 3 V to $-10$ V in steps of 1 V. (d) Schematic diagram illustrating 2D-VRH, PFE, and TAT processes.