Experimental Demonstration of a Superconductor SFQ-Based ADC for High-Frequency Signal Acquisition

TL;DR

This work tackles the challenge of achieving high-frequency, low-power analog-to-digital conversion at cryogenic temperatures by proposing a fully integrated SFQ-based ADC on a single chip. The approach combines two digital SQUID modulators with distinct sensitivities, a majority-voting scheme to suppress errors, and two on-chip readout paths—a fast asynchronous flash counter and a noise-robust synchronous cumulative counter. Experimental validation demonstrates correct operation of the TFF counters, integration with the modulator, and consistent bidirectional counting, supported by a cryogenic testbed at $T \,=\, 4.2$ K. The resulting architecture offers flexible, scalable cryogenic digital readout with potential applications in quantum sensing and cryogenic data acquisition, enabling on-chip DSP compatibility and reduced room-temperature hardware.

Abstract

Superconducting quantum interference devices (SQUIDs) are among the most sensitive sensors, offering high precision through their well-defined flux-voltage characteristics. Building on this sensitivity, we designed, fabricated, and experimentally demonstrated a superconducting single flux quantum (SFQ)-based analog-to-digital converter (ADC) capable of detecting small variations in input current signals at high frequencies and converting them into SFQ pulse trains. To improve robustness and reduce errors, the design incorporates a majority circuit and two types of counters: asynchronous toggle flip-flop-based and synchronous cumulative-based, at the cryogenic stage. The counter collects the SFQ pulse train and converts it into a binary number, simplifying downstream digital readout. The circuits were implemented using the AIST CRAVITY (QuFab) HSTP process and successfully tested in our cryocooler system, validating both the design methodology and operation. This approach helps build a fully integrated system that combines digital SQUID functionality with cryogenic readout circuits on a single chip.

Figures (19)

• Figure 1: Block diagram of the proposed SFQ-based ADC architecture. The system comprises two digital SQUID modulators with distinct sensitivities and two digital processing units. The different sensitivities are achieved by tuning circuit parameters within a unified hardware platform. The processing units perform complementary functions: the flash counter is an asynchronous structure implemented with toggle flip-flops (TFFs) for rapid SFQ pulse counting, while the cumulative counter is a synchronous unit that includes an up/down counter and an averaging stage to enhance noise resilience. Selection between the modulators and processing units is managed through passive transmission line (PTL) links. Since PTLs do not convey bias currents, they define separate bias domains, allowing selective biasing of the desired circuit blocks.
• Figure 2: Circuit schematic of the digital SQUID designed using parameters from the HSTP process. The superconducting loop contains two Josephson junctions and a single inductor. Depending on the direction of the circulating current, either B1 or B2 switches release an SFQ pulse that relaxes the loop energy. The resulting current propagates through L1 or L2 and activates B3 or B4, which drive the digital processing stage. Each junction is resistively shunted so that $I_cR_n = 0.4$.
• Figure 3: Simulation result for Modulator-1. The input signal induces a circulating current in the loop, generating a screening current that opposes the applied flux. Once the screening current reaches its critical limit, one of the junctions switches to release an SFQ pulse, reducing the stored magnetic energy. Each switching corresponds to a quantized $2\pi$ phase change and represents one SFQ pulse transmitted to the subsequent logic stage. The pulse timing depends on the input slope: a steeper input slope produces faster pulse emission. In this example, let $m_1$ and $m_2$ denote the positive and negative input slopes, respectively, with $m_1 = 2m_2$. As a result, the time interval between two negative-slope pulses ($\Delta t_2$) is twice the interval between positive-slope pulses ($\Delta t_1$). The figure also shows the normalized phase variations in J1 and J2 as a function of the external flux, where each $2\pi$ increment indicates a single SFQ switching event. These results demonstrate how the rate of change of the input signal maps directly to the frequency of the SFQ pulses.
• Figure 4: Simulation result for Modulator-2. The larger loop inductance increases the sensitivity to small magnetic flux variations, resulting in more frequent SFQ switching events. In this example, Modulator-2 generates eight SFQ pulses for the same input signal that produces three pulses in Modulator-1. The normalized phase traces of J1 and J2 show more frequent $2\pi$ phase transitions, illustrating the enhanced flux resolution of the circuit. Although higher sensitivity comes with slightly reduced bandwidth and greater noise susceptibility, Modulator-2 provides finer temporal quantization of the input waveform, demonstrating the tunable balance between sensitivity and speed.
• Figure 5: Effect of noise on digital SQUID outputs for different input slopes. Slope values: $m_1 = 1\,\mathrm{mA/ns}$, $m_2 = -0.5\,\mathrm{mA/ns}$, $m_3 = 0.67\,\mathrm{mA/ns}$, $m_4 = -2\,\mathrm{mA/ns}$, $m_5 = 1.5\,\mathrm{mA/ns}$, $m_6 = -0.75\,\mathrm{mA/ns}$. The relation between the absolute values is $|m_2| < |m_6| < |m_1| < |m_3| < |m_5| < |m_4|$. The noisy input is applied to three SQUIDs, and the effect of noise is observed for different slopes. The distortion is more pronounced for lower slope magnitudes.