Decoding Correlated Errors in Quantum LDPC Codes
Arshpreet Singh Maan, Francisco-Garcia Herrero, Alexandru Paler, Valentin Savin
TL;DR
This work addresses decoding correlated errors in quantum LDPC codes under circuit-level noise by introducing GARI, a graph augmentation and rewiring framework that eliminates 4-cycles involving $Y$-type errors to enable effective belief-propagation-like inference. By reformulating the decoding problem with an augmented matrix $ ilde D_{XYZ}$ and employing a normalized min-sum decoder with a hybrid serial-layered schedule, the authors achieve high accuracy with low latency, particularly when using a 24-decoder ensemble. On bivariate bicycle codes of distances 6, 10, and 12, GARI-NMS matches or surpasses prior best decoders (e.g., BPOSD, XYZ-Relay-BP) and, for distance-12, attains a logical error rate per round of $(6.70 ext{±} 1.93) imes 10^{-9}$ at a physical error rate of $10^{-3}$. FPGA implementations demonstrate real-time decoding with an average per-round latency of 273 ns and sub-microsecond latency in 99.99% of cases, signaling a viable path to practical fault-tolerant quantum computation.
Abstract
We introduce a decoding framework for correlated errors in quantum LDPC codes under circuit-level noise. The core of our approach is a graph augmentation and rewiring for interference (GARI) method, which modifies the correlated detector error model by eliminating 4-cycles involving Y-type errors, while preserving the equivalence of the decoding problem. We test our approach on the bivariate bicycle codes of distances 6, 10, and 12. A normalized min-sum decoder with a hybrid serial-layered schedule is applied on the transformed graph, achieving high accuracy with low latency. Performance is further enhanced through ensemble decoding, where 24 randomized normalized min-sum decoders run in parallel on the transformed graph, yielding the highest reported accuracy (on par with XYZ-Relay-BP) with unprecedented speed for the tested codes under uniform depolarizing circuit level noise. For the distance 12 (gross) code, our approach yields a logical error rate of $(6.70 \pm 1.93) \times 10^{-9}$ at a practical physical error rate of $10^{-3}$. Furthermore, preliminary FPGA implementation results show that such high accuracy can be achieved in real time, with a per-round average decoding latency of 273 ns and sub-microsecond latency in 99.99% of the decoding instances.
