Accelerated Feature Detectors for Visual SLAM: A Comparative Study of FPGA vs GPU

TL;DR

The paper investigates hardware acceleration for feature detectors within a Visual SLAM pipeline on energy-constrained edge platforms by comparing FPGA- and GPU-accelerated implementations of FAST, Harris, and SuperPoint in an ICE-BA–based V-SLAM system. On Nvidia Jetson Orin and AMD Versal, non-learning detectors favor GPU implementations for runtime and energy efficiency, while learning-based SuperPoint can benefit from FPGA acceleration, achieving up to 3.1× faster runtimes and 1.4× better energy efficiency in some cases. The study demonstrates that FPGA-accelerated ICE-BA can match GPU runtimes in several sequences, though GPU-accelerated ICE-BA generally yields higher accuracy. Moreover, enabling hardware acceleration for feature detection can decrease the frequency of global bundle adjustments, enhancing overall V-SLAM performance without sacrificing accuracy. These findings inform design choices for edge V-SLAM systems, illustrating how detector type and platform architecture jointly affect end-to-end performance and energy efficiency.

Abstract

Feature detection is a common yet time-consuming module in Simultaneous Localization and Mapping (SLAM) implementations, which are increasingly deployed on power-constrained platforms, such as drones. Graphics Processing Units (GPUs) have been a popular accelerator for computer vision in general, and feature detection and SLAM in particular. On the other hand, System-on-Chips (SoCs) with integrated Field Programmable Gate Array (FPGA) are also widely available. This paper presents the first study of hardware-accelerated feature detectors considering a Visual SLAM (V-SLAM) pipeline. We offer new insights by comparing the best GPU-accelerated FAST, Harris, and SuperPoint implementations against the FPGA-accelerated counterparts on modern SoCs (Nvidia Jetson Orin and AMD Versal). The evaluation shows that when using a non-learning-based feature detector such as FAST and Harris, their GPU implementations, and the GPU-accelerated V-SLAM can achieve better run-time performance and energy efficiency than the FAST and Harris FPGA implementations as well as the FPGA-accelerated V-SLAM. However, when considering a learning-based detector such as SuperPoint, its FPGA implementation can achieve better run-time performance and energy efficiency (up to 3.1$\times$ and 1.4$\times$ improvements, respectively) than the GPU implementation. The FPGA-accelerated V-SLAM can also achieve comparable run-time performance compared to the GPU-accelerated V-SLAM, with better FPS in 2 out of 5 dataset sequences. When considering the accuracy, the results show that the GPU-accelerated V-SLAM is more accurate than the FPGA-accelerated V-SLAM in general. Last but not least, the use of hardware acceleration for feature detection could further improve the performance of the V-SLAM pipeline by having the global bundle adjustment module invoked less frequently without sacrificing accuracy.

Figures (7)

• Figure 1: Profiling of the ICE-BA localization thread on an Nvidia Jetson Orin SoC, an Intel Xeon workstation, and an AMD VCK190 SoC using only the processors and Machine Hall sequences. Best viewed in color.
• Figure 2: High-level overview of the hardware-accelerated ICE-BA pipeline. Best viewed in color.
• Figure 3: Speedups and energy efficiency improvements of different FAST and Harris accelerators w.r.t OpenCV FAST + Xeon. Best viewed in color.
• Figure 4: Run-time and energy efficiency of different SuperPoint accelerators. Best viewed in color.
• Figure 5: Speedups and energy efficiency improvements of ICE-BA integrated with different FAST and Harris accelerators w.r.t ICE-BA + OpenCV FAST + Xeon. Best viewed in color.