Integration of imprint-free and low coercivity ferroelectric BaTiO3 thin films on silicon

TL;DR

The paper addresses the integration of BaTiO3 on silicon, a CMOS-relevant challenge due to large thermal and lattice mismatch. It introduces a SSTO buffer as a strain-mediating pseudo-substrate to relax thermal strain and impose moderate compressive strain, stabilizing out-of-plane polarization. Key results include imprint-free, low-coercivity switching with $P_r \approx 20\,\mu C\,cm^{-2}$, leakage-free operation, endurance beyond $10^{10}$ cycles, and a two-regime switching dynamics with activation fields around $E_0 \approx 533.8\,kV/cm$ (low freq) and $E_0 \approx 299.6\,kV/cm$ (high freq). The work enables silicon-compatible, low-power ferroelectric devices such as nonvolatile memories and FTJs by delivering high-quality epitaxy with robust switching.

Abstract

Highly-crystalline ferroelectric oxides integrated on Si hold great promise for energy-efficient memory and logic technologies. Exploiting epitaxial strain engineering in these materials is, however, severely hampered on Si, where the large structural mismatch often results in an inferior interfacial quality and causes a degradation of the ferroelectric switching characteristics. In this work, we present the growth of single-crystalline BaTiO3 thin films on Si, exhibiting imprint-free switching, low coercivity, high remanent polarization, and no fatigue for over $10^{10}$ switching cycles. We accomplish this via the insertion of a SrSn1-xTixO3 layer on SrTiO3-buffered Si. This layer serves as a pseudo substrate that alleviates the thermal strain that the Si substrates imposes on the BaTiO3 layer, while simultaneously providing moderate compressive strain that stabilizes a pure out-of-plane polarization. Thus, our work paves the way toward the fabrication of Si-compatible, low-power-consuming ferroelectric devices for non-volatile memory applications.

Figures (4)

• Figure 1: Structural and local ferroelectric characterization of BaTiO3 (BTO) on SrSn0.45Ti0.55O3 (SSTO)-buffered SrTiO3 (STO). a) Illustration of the heterostructure BTO/SRO/SSTO grown on TiO2-terminated STO. b) Symmetric XRD $\theta\text{--}2\theta$ scan of the heterostructure around the STO 002 peak. c) XRD reciprocal space map around the STO 103 reflection. d) 5$\times$5µm atomic force microscopy topographic image. Vertical piezoresponse force microscopy (PFM) phase e) and amplitude f) responses across an electrically poled box-in-box region.
• Figure 2: Structural and local ferroelectric characterization of BTO on Si. a) Illustration of the BTO/SRO/SSTO heterostructure grown on STO-buffered Si (001). b) Symmetric XRD $\theta\text{--}2\theta$ scan of the heterostructure with the inset showing the in-situ acquired integrated RHEED time trace during BTO growth. c) XRD reciprocal space map around the SSTO 103 reflection, showing that the SSTO lattice parameters are close to those of GdScO3 (known to provide optimal strain conditions for out-of-plane polarized BTO). d) 5$\times$5µm atomic force microscopy topographic image of the BTO surface. Vertical piezoresponse force microscopy phase e) and amplitude f) responses across the electrically poled box-in-box region.
• Figure 3: Macroscopic ferroelectric characterization of BTO on Si. a) Polarization-electric field hysteresis loops measured at 5kHz for various electric field amplitudes, showing lack of imprint. b) Switching current profiles corresponding to the loops in a). c) Frequency-dependent hysteresis loops over the range 0.6Hz--5kHz showing coercive voltages ($V_\mathrm{c}$) in the range of $0.12-$0.55V. d) Coercive field ($E_\mathrm{c}$) as a function of frequency extracted from c). The inset shows the Merz-law fitting of the same dataset.
• Figure 4: Robustness of the BTO switching characteristics. a) PUND hysteresis loops and corresponding switching current profiles measured at 2kHz. b) Ferroelectric cycling endurance over $10^{10}$ cycles measured with a voltage amplitude of 4V and a frequency of 2kHz. The inset show the PUND loops obtained after 1, $10^{8}$, and $10^{10}$ cycles. c) Dynamic hysteresis loops for BTO films on Si with different thickness. d) Literature comparison of the device imprint and $V_\mathrm{c}$ in BTO thin films on Si substrates, with the vertical axis indicating the reference numbers.