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RFSoC Based LLRF System Design at ALS

Qiang Du, Shreeharshini Murthy, Victoria Moore, Angel Jurado Lopez, Michael Chin, Shree Subhasish Basak, David Nett, Benjamin Flugstad

TL;DR

This work presents a RFSoC-based direct-sampling LLRF system for the ALS that unifies control across multiple RF frequencies (125 MHz, 500 MHz, 3 GHz) through a modular, open-source platform. It combines multi-tile synchronization, deterministic latency, digital up/down conversion, AWG/ADC capabilities, in-pulse closed-loop control, timing, and EPICS integration within a configurable RF frontend. Hardware (LBL208/LXZU47DR), firmware (clocking, MTS, DSP), and software (PYNQ overlays, EPICS IOC) are designed to support Linac and SHB requirements, with bench results showing end-to-end latency below ~400 ns, DAC phase jitter around ~80 fs, SFDR ~90 dB, and ADC crosstalk >75 dB. The architecture is scalable and suitable for ALS upgrades and similar facilities, enabling precise, low-noise LLRF operation across diverse RF bands through an open, modular approach.

Abstract

The Advanced Light Source (ALS) at LBNL is upgrading several LLRF systems for its Linac and Sub-Harmonic Bunchers, where it is desired to have a unified LLRF system design to support various RF frequencies (at 125MHz, 500MHz and 3GHz) and configurations. This paper demonstrates an open-source, direct sampling RFSoC based LLRF system design, featuring: sample-to-sample Multi-Tile Synchronization, deterministic latency, digital up/down conversion, arbitrary waveform generation and acquisition, in-pulse closed loop control, timing and EPICS integration, modular RF frontend and hardware designs. Measured RF characteristics show that the RFSoC based LLRF system is able to meet the system requirements.

RFSoC Based LLRF System Design at ALS

TL;DR

This work presents a RFSoC-based direct-sampling LLRF system for the ALS that unifies control across multiple RF frequencies (125 MHz, 500 MHz, 3 GHz) through a modular, open-source platform. It combines multi-tile synchronization, deterministic latency, digital up/down conversion, AWG/ADC capabilities, in-pulse closed-loop control, timing, and EPICS integration within a configurable RF frontend. Hardware (LBL208/LXZU47DR), firmware (clocking, MTS, DSP), and software (PYNQ overlays, EPICS IOC) are designed to support Linac and SHB requirements, with bench results showing end-to-end latency below ~400 ns, DAC phase jitter around ~80 fs, SFDR ~90 dB, and ADC crosstalk >75 dB. The architecture is scalable and suitable for ALS upgrades and similar facilities, enabling precise, low-noise LLRF operation across diverse RF bands through an open, modular approach.

Abstract

The Advanced Light Source (ALS) at LBNL is upgrading several LLRF systems for its Linac and Sub-Harmonic Bunchers, where it is desired to have a unified LLRF system design to support various RF frequencies (at 125MHz, 500MHz and 3GHz) and configurations. This paper demonstrates an open-source, direct sampling RFSoC based LLRF system design, featuring: sample-to-sample Multi-Tile Synchronization, deterministic latency, digital up/down conversion, arbitrary waveform generation and acquisition, in-pulse closed loop control, timing and EPICS integration, modular RF frontend and hardware designs. Measured RF characteristics show that the RFSoC based LLRF system is able to meet the system requirements.
Paper Structure (32 sections, 15 figures, 4 tables)

This paper contains 32 sections, 15 figures, 4 tables.

Table of Contents

  1. Introduction
  2. System requirements and Overview
  3. Linac LLRF system requirements
  4. Buncher RF system requirements
  5. RFSoC LLRF system architecture
  6. LLRF Requirements
  7. System architecture design
  8. System implementation and characteristics
  9. RF performance evaluation
  10. DAC phase noise
  11. DAC output spectrum
  12. ADC characteristics
  13. ADC crosstalk
  14. Hardware Design
  15. Analog Frontend
  16. ...and 17 more sections

Figures (15)

  • Figure 1: Roadmap of digital LLRF systems at ALS in LBNL. Diamond marks planned RFSoC based LLRF systems.
  • Figure 2: RFSoC LLRF system architecture
  • Figure 3: RF output phase noise measurements with RMS jitter integrated over [1Hz, 1MHz]
  • Figure 4: DAC output spectrum at 500 MHz, SFDR is about 90 dB within 200kHz span, 100Hz RBW
  • Figure 5: Modular Analog Front-End design
  • ...and 10 more figures