ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

TL;DR

ShuffleV introduces a moving-target defense at the microarchitectural level to mitigate EM side-channel attacks by nondeterministically shuffling instruction execution with an optional dummy-instruction layer. Implemented on the Ibex RISC-V core, it provides multiple configuration options and a simulator for rapid security/performance evaluation, and is demonstrated on FPGA against AES-128 and neural network inference with favorable overhead and strong CEMA resistance. Unlike software-only or bespoke hardware solutions, ShuffleV offers automatic protection without code changes or recompilation, and maintains compatibility as a drop-in replacement in diverse SoCs. The work highlights practical impact for secure edge devices by enabling robust, low-overhead protection of cryptographic and NN workloads against EM-based leakage.

Abstract

The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Many recent works have demonstrated successful attacks leveraging such side-channels to extract the confidentiality of diverse applications, such as the key of cryptographic algorithms and the hyperparameter of neural network models. This paper proposes ShuffleV, a microarchitecture defense strategy against EM Side-Channel Attacks (SCAs). ShuffleV adopts the moving target defense (MTD) philosophy, by integrating hardware units to randomly shuffle the execution order of program instructions and optionally insert dummy instructions, to nullify the statistical observation by attackers across repetitive runs. We build ShuffleV on the open-source RISC-V core and provide six design options, to suit different application scenarios. To enable rapid evaluation, we develop a ShuffleV simulator that can help users to (1) simulate the performance overhead for each design option and (2) generate an execution trace to validate the randomness of execution on their workload. We implement ShuffleV on a Xilinx PYNQ-Z2 FPGA and validate its performance with two representative victim applications against EM SCAs, AES encryption, and neural network inference. The experimental results demonstrate that ShuffleV can provide automatic protection for these applications, without any user intervention or software modification.

Figures (26)

• Figure 1: Our setup for performing EM measurements.
• Figure 2: Histogram of the length of EM traces collected from the 5i5w MAC operation (top) and the AES-128 encryption (bottom) programs run on the Secure Ibex core. Purple dashed lines indicate the minimum and maximum lengths of traces used for the attack.
• Figure 3: Normalized execution time of the Secure Ibex with dummy instruction interval (DII) = 8 and 16 compared to the Ibex core on MAC and AES-128 workload (lower is better).
• Figure 4: ShuffleV's high level diagram of the instruction fetch and shuffle process.
• Figure 5: Instruction selection scheme in ShuffleV.