High-Parallel FPGA-Based Discrete Simulated Bifurcation for Large-Scale Optimization

TL;DR

This work tackles large-scale combinatorial optimization by mapping problems to the Ising model and implementing a high-parallel, open-source FPGA architecture for discrete simulated bifurcation (dSB) with heated (HbSB) and ballistic (bSB) variants. It analyzes fixed-point versus floating-point representations, integrates the external field $h$ via an augmented matrix $J^*$, and realizes a scalable MMTE-based hardware design with three parallelization degrees (Pc, Pr, Pb). The proof-of-concept on a 256-spin instance demonstrates competitive speed and accuracy, validating max-cut and knapsack benchmarks and highlighting memory-bound limitations and initialization overhead. The work provides a practical, open-resource path toward hardware-accelerated quantum-inspired optimization and potential ASIC deployment, with future improvements addressing data dependencies, RNG-based initialization, and problem preconditioning.

Abstract

Combinatorial Optimization (CO) problems exhibit exponential complexity, making their resolution challenging. Simulated Adiabatic Bifurcation (aSB) is a quantum-inspired algorithm to obtain approximate solutions to largescale CO problems written in the Ising form. It explores the solution space by emulating the adiabatic evolution of a network of Kerr-nonlinear parametric oscillators (KPOs), where each oscillator represents a variable in the problem. The optimal solution corresponds to the ground state of this system. A key advantage of this approach is the possibility of updating multiple variables simultaneously, making it particularly suited for hardware implementation. To enhance solution quality and convergence speed, variations of the algorithm have been proposed in the literature, including ballistic (bSB), discrete (dSB), and thermal (HbSB) versions. In this work, we have comprehensively analyzed dSB, bSB, and HbSB using dedicated software models, evaluating the feasibility of using a fixed-point representation for hardware implementation. We then present an opensource hardware architecture implementing the dSB algorithm for Field-Programmable Gate Arrays (FPGAs). The design allows users to adjust the degree of algorithmic parallelization based on their specific requirements. A proof-of-concept implementation that solves 256-variable problems was achieved on an AMD Kria KV260 SoM, a low-tier FPGA, validated using well-known max-cut and knapsack problems.

Figures (13)

• Figure 1: Algorithms comparison for a 2-node max-cut problem. The trajectories of the oscillators' network over time are shown by the white lines. The potential energies at the final time are also depicted ($V_{aSB}$, $V_{bSB}$ and $V_{dSB}$).
• Figure 2: Position and momentum variable evolutions of a two oscillators system with anti-ferromagnetic interaction.
• Figure 3: Cumulative distribution obtained for a http://artemisa.unicauca.edu.co/ johnyortega/instances_01_KP/ considering fixed and floating point implementation of dSB, bSB and HbSB.
• Figure 4: Comparison of the evolution of the cut value over time with the 800-spin G7 max-cut problem of the https://web.stanford.edu/ yyye/yyye/Gset/, using $\Delta t=1.0$, $\gamma=0.5$ and $n_\textrm{steps} = 10^4$, for dSB, bSB and HbSB.
• Figure 5: At the top, the timing of the sequential algorithm is illustrated. In the second timing, MM is sped up by a factor $\mathbf{P_c}\cdot \mathbf{P_r}$ after unrolling. In the third timing, MM and TE overlapping is implemented. On the bottom, MMTE replication is also applied with $\mathbf{P_b}$ equal to three.