A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems

TL;DR

The paper tackles inefficiencies of descriptor-based DMACs for irregular, small transfers by introducing a compact 256-bit descriptor with chaining and a speculative prefetching mechanism. This DMAC is integrated into a 64-bit Linux-capable RISC-V CVA6 SoC and validated on Kintex FPGA, demonstrating a 1.66x reduction in transfer-launch latency and up to 3.6x bus utilization gains in deep memory configurations compared to a LogiCORE IP DMA, with significant reductions in LUTs and FFs and no BRAMs in the base design. The architecture combines a lightweight DMA frontend, a high-performance backend, and a Linux driver, offering scalable area and timing characteristics (synthesized beyond 1.4 GHz in a 12 nm process). Overall, the approach provides fast, flexible DMA for irregular data transfers in heterogeneous memory systems and is released as open-source for broader adoption in RISC-V Linux ecosystems.

Abstract

With the ever-growing heterogeneity in computing systems, driven by modern machine learning applications, pressure is increasing on memory systems to handle arbitrary and more demanding transfers efficiently. Descriptor-based direct memory access controllers (DMACs) allow such transfers to be executed by decoupling memory transfers from processing units. Classical descriptor-based DMACs are inefficient when handling arbitrary transfers of small unit sizes. Excessive descriptor size and the serialized nature of processing descriptors employed by the DMAC lead to large static overheads when setting up transfers. To tackle this inefficiency, we propose a descriptor-based DMAC optimized to efficiently handle arbitrary transfers of small unit sizes. We implement a lightweight descriptor format in an AXI4-based DMAC. We further increase performance by implementing a low-overhead speculative descriptor prefetching scheme without additional latency penalties in the case of a misprediction. Our DMAC is integrated into a 64-bit Linux-capable RISC-V SoC and emulated on a Kintex FPGA to evaluate its performance. Compared to an off-the-shelf descriptor-based DMAC IP, we achieve 1.66x less latency launching transfers, increase bus utilization up to 2.5x in an ideal memory system with 64-byte-length transfers while requiring 11% fewer lookup tables, 23% fewer flip-flops, and no block RAMs. We can extend our lead in bus utilization to 3.6x with 64-byte-length transfers in deep memory systems. We synthesized our DMAC in GlobalFoundries' GF12LP+ node, achieving a clock frequency of over 1.44 GHz while occupying only 49.5 kGE.

Figures (5)

• Figure 1: Overview of the , containing request logic with internal registers for configuration and read logic to fetch the descriptor, and feedback logic to update the system once the backend completes the transfer.
• Figure 2: Integration of our into the CVA6 . The two manager interfaces, after arbitration, as well as the subordinate configuration port of the , are connected to the 's interconnect. The line is connected to the platform's .
• Figure 3: The testbench setup; the has its two manager interfaces connected to a fair round-robin arbiter (RR), which in turn is connected to a latency-configurable memory system. Descriptors are loaded into the memory using backdoor access and are launched via the 's subordinate configuration interface.
• Figure 4: steady-state bus utilization given a prefetch hit rate of 100% in memory systems featuring various latencies.
• Figure 5: steady-state bus utilization in the case of the DDR3 main memory with speculation misses; speculation configuration.