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Digital Low-Level RF system for the Linac Electronics Modernization Plan at LCLS

Nashat Sawai, Jorge Diaz Cruz, Andy Benwell, Sonya Hoobler, Qiang Du, Shreeharshini Murthy, Larry Doolittle

TL;DR

The paper addresses aging control hardware in the SLAC NC LINAC by deploying an LLMRF upgrade (LEMP) that uses the Marble FPGA carrier and Zest+ digitizer, aligned with LCLS-II LLRF concepts to enhance reliability and performance. The approach integrates hardware, firmware, and software to deliver coherent timing, LO generation via a $2.856$ GHz RF chain, down/up-conversion to $25.5$ MHz/$93.5$ MHz IFs, and DSP-based control, all anchored by Bedrock and PicoRV32 components. Key contributions include a compact, modular LLRF chassis with an integrated rear I/O, DSP architecture, and EPICS-driven software, plus initial demonstrations at station 26-3 showing stable RF generation, interlocks, and waveform capture with sub-$40$ fs phase jitter. The work significantly advances modernizing the NC linac while enabling smoother integration with LCLS controls and future pulsed operation, offering a scalable path to upgrade additional stations.

Abstract

The LCLS began operations in 2009, utilizing SLAC's normal-conducting (NC) LINAC, which features control equipment dating back to the 1960s and 1980s. The Linac Electronics Modernization Plan (LEMP) aims to replace the legacy control equipment with a system based on the open-source Marble carrier board and Zest+ digitizer board, both of which are used in the LCLS-II HE LLRF system. Adaptation of the LLRF system developed for the continuous-wave (CW) superconducting RF (SRF) LCLS-II to the short-RF pulse NC LCLS includes leveraging the knowledge and experience gained from recent LLRF projects at SLAC and efficiently reusing the core functionality of the hardware and code base developed for previous projects, in collaboration with LBNL, FNAL and JLAB. A prototype has been deployed and tested at station 26-3, demonstrating RF generation/control, interlocks, triggers, and waveform capture. Here, we describe the hardware, firmware and software infrastructure, highlight key features, and present initial test results.

Digital Low-Level RF system for the Linac Electronics Modernization Plan at LCLS

TL;DR

The paper addresses aging control hardware in the SLAC NC LINAC by deploying an LLMRF upgrade (LEMP) that uses the Marble FPGA carrier and Zest+ digitizer, aligned with LCLS-II LLRF concepts to enhance reliability and performance. The approach integrates hardware, firmware, and software to deliver coherent timing, LO generation via a GHz RF chain, down/up-conversion to MHz/ MHz IFs, and DSP-based control, all anchored by Bedrock and PicoRV32 components. Key contributions include a compact, modular LLRF chassis with an integrated rear I/O, DSP architecture, and EPICS-driven software, plus initial demonstrations at station 26-3 showing stable RF generation, interlocks, and waveform capture with sub- fs phase jitter. The work significantly advances modernizing the NC linac while enabling smoother integration with LCLS controls and future pulsed operation, offering a scalable path to upgrade additional stations.

Abstract

The LCLS began operations in 2009, utilizing SLAC's normal-conducting (NC) LINAC, which features control equipment dating back to the 1960s and 1980s. The Linac Electronics Modernization Plan (LEMP) aims to replace the legacy control equipment with a system based on the open-source Marble carrier board and Zest+ digitizer board, both of which are used in the LCLS-II HE LLRF system. Adaptation of the LLRF system developed for the continuous-wave (CW) superconducting RF (SRF) LCLS-II to the short-RF pulse NC LCLS includes leveraging the knowledge and experience gained from recent LLRF projects at SLAC and efficiently reusing the core functionality of the hardware and code base developed for previous projects, in collaboration with LBNL, FNAL and JLAB. A prototype has been deployed and tested at station 26-3, demonstrating RF generation/control, interlocks, triggers, and waveform capture. Here, we describe the hardware, firmware and software infrastructure, highlight key features, and present initial test results.

Paper Structure

This paper contains 12 sections, 8 figures, 3 tables.

Table of Contents

  1. Introduction
  2. HARDWARE DESIGN
  3. Frequency and Local Oscillator Configuration
  4. Analog RF Front-End
  5. Rear I/O Board
  6. Chassis Implementation
  7. Firmware Design
  8. DSP structure
  9. Software
  10. Prototype Test
  11. Conclusions
  12. Acknoweldgements

Figures (8)

  • Figure 1: LEMP sector upgrade.
  • Figure 2: RF front-end downconverter module and enclosure.
  • Figure 3: Rear I/O board.
  • Figure 4: Prototype LEMP LLRF chassis.
  • Figure 5: LLRF system architecture
  • ...and 3 more figures