Fabrication of an atom chip for Rydberg atom-metal surface interaction studies

TL;DR

The work addresses the challenge of studying $^{87}$Rb Rydberg atoms near metal surfaces by designing an atom chip that can stably position cold atoms at well-defined distances from a Au surface while suppressing stray electric fields. The approach combines five microfabricated trapping wires, a planarization polyimide dielectric, and a thin Au electrostatic shield to minimize patch-field effects and to provide a reflective surface for MOT, enabling controlled Rydberg excitation near the surface. Key contributions include a detailed fabrication protocol with planarization performance (≈85% DOP), analysis of diffusion-related metallization stability (favoring Ti-based stacks), and quantitative predictions for patch-field detectability via Stark broadening of high-n transitions (e.g., $5d_{5/2}\to50f_{7/2}$) at distances around 100 μm. The study establishes a practical platform for mapping near-surface electric fields and for investigating image-charge interactions and Lennard-Jones shifts in Rydberg atoms, with implications for quantum devices and surface-sensitive spectroscopy.

Abstract

An atom chip has been fabricated for the study of interactions between $^{87}$Rb Rydberg atoms and a Au surface. The chip tightly confines cold atoms by generating high magnetic field gradients using microfabricated current-carrying wires. These trapped atoms may be excited to Rydberg states at well-defined atom-surface distances. For the purpose of Rydberg atom-surface interaction studies, the chip has a thermally evaporated Au surface layer, separated from the underlying trapping wires by a planarizing polyimide dielectric. Special attention was paid to the edge roughness of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

Figures (8)

• Figure 1: Schematic of the atom chip. (a) Trapping wires (b) Magnified view of the end of the center wire strip is shown at right. The widths of the center wires and spaces are $7 \mathop{\rm \mu m}\nolimits$, but are exaggerated here for clarity. (c) Cross section of the chip.
• Figure 2: Patterning of polyimide planarization layer: a) coat and cure polyimide; b) sputter Al; c) pattern positive photoresist over Al; d) wet etch Al using photoresist as mask, then remove photoresist; e) reactive ion etch (RIE) polyimide using Al as mask; f) wet etch to remove remove Al mask.
• Figure 3: Change in resistance in the center wire with Cr/Au, Ti/Au, Cr/Pd/Au and Ti/Pd/Au metallizations after subjecting to polyimide cure cycles. The solid lines are to aid the eye.
• Figure 4: SEM image of a wire edge. To the right of the wire is a thin layer of metal that reached the wafer at a non-normal incident angle and passed beneath the undercut of the photoresist. This film exists exhibits the characteristics of island formation in preliminary thin film growth Liu:1997.
• Figure 5: (a) Stylus profilometer (Dektak) scan of polyimide surface over the five center wires. Polyimide was coated in three layers with full cure between each. (b) SEM image of an etched polyimide film demonstrating the extent of planarization over the central trapping wires.