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Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)

Omar Abdelrahman, Gianluca Aglieri Rinella, Luca Aglietta, Giacomo Alocco, Matias Antonelli, Roberto Baccomi, Francesco Barile, Pascal Becht, Franco Benotto, Stefania Maria Beolè, Marcello Borri, Daniela Bortoletto, Naseem Bouchhar, Giuseppe Eugenio Bruno, Matthew Daniel Buckland, Szymon Bugiel, Paolo Camerini, Francesca Carnesecchi, Marielle Chartier, Domenico Colella, Angelo Colelli, Giacomo Contin, Giuseppe De Robertis, Wenjing Deng, Antonello Di Mauro, Vittorio Di Trapani, Maurice Donner, Ana Dorda Martin, Piotr Dorosz, Floarea Dumitrache, Lars Döpper, Gregor Hieronymus Eberwein, Domenico Elia, Simone Emiliani, Laura Fabbietti, Tommaso Fagotto, Xiaochao Fang, Henrik Fribert, Roman Gernhäuser, Piero Giubilato, Laura Gonella, Karl Gran Grodaas, Ola Slettevoll Groettvik, Vladimir Gromov, Malte Grönbeck, Philip Hauer, Hartmut Hillemanns, Guen Hee Hong, Yu Hu, Minyoung Chris Hwang, Marc Alain Imhoff, Barbara Jacak, Daniel Matthew Jones, Antoine Junique, Filip Křížek, Jetnipit Kaewjai, Anouk Kaiser, Jesper Karlsson Gumprecht, Markus Keil, Bernhard Ketzer, Jiyoung Kim, Lena Kirchner, Kritsada Kittimanapun, Alex Kluge, Chinorat Kobdaj, Artem Kotliarov, Thanushan Kugathasan, Marc König, Paola La Rocca, Natthawut Laojamnongwong, Lukas Lautner, Corentin Lemoine, Long Li, Beatrice Eva Liang-Gilman, Francesco Licciulli, Sanghoon Lim, Bong-Hwi Lim, Jian Liu, Flavio Loddo, Matteo Lupi, Magnus Mager, Philipp Mann, Georgios Mantzaridis, Davide Marras, Paolo Martinengo, Silvia Masciocchi, Annalisa Mastroserio, Soniya Mathew, Serena Mattiazzo, Marius Wilm Menzel, Nicola Minafra, Frederic Morel, Alice Mulliri, Anjali Ila Nambrath, Rajendra Nath Patra, Iaroslav Panasenko, Styliani Paniskaki, Caterina Pantouvakis, Cosimo Pastore, Stefania Perciballi, Francesco Piro, Adithya Pulli, Alexander Rachev, Alexander Rachevski, Ivan Ravasenga, Felix Reidt, Michele Rignanese, Giacomo Ripamonti, Isabella Sanna, Valerio Sarritzu, Umberto Savino, Iain Sedgwick, Serhiy Senyukov, Danush Shekar, Sabyasachi Siddhanta, David Silvermyr, Walter Snoeys, Joey Staa, Alessandro Sturniolo, Miljenko Šuljić, Timea Szollosova, Daniel Tapia Takaki, Livia Terlizzi, Nicolas Tiltmann, Antonio Trifirò, Christina Tsolanta, Rosario Turrisi, Berkin Ulukutlu, Gianluca Usai, Isabelle Valin, Giovanni Vecil, Pedro Vicente Leitao, Anna Villani, Chunzheng Wang, Zhenyu Ye, Emma Rose Yeats, Asli Yelkenci, Zijun Zhao, Alessandra Zingaretti

TL;DR

The paper addresses the challenge of fabricating large, ultra-thin MAPS detectors for the ALICE ITS3 upgrade via wafer-scale stitching. It presents the MOSS prototype as a full-scale demonstration of stitching, interconnects, and large-area pixel readout, including extensive lab and in-beam characterisation, irradiation tests, and SEE studies. Key results show a robust functional yield (≈98% when excluding powering and readout-specific issues), near-target detection efficiency and fake-hit rates, and spatial resolution meeting ITS3 aspirations for an 18 µm pitch. The findings establish the feasibility of stitched wafer-scale MAPS for ITS3, while guiding design optimisations for power distribution, readout architecture, and SEE mitigation in the final sensor implementation, with significant implications for truly cylindrical, low-mass vertex detectors in high-energy physics.

Abstract

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 $\times$ 25.9 cm, thinned to 50 $μ$m. The chip architecture, in-pixel front-end, laboratory and in-beam characterisation, susceptibility to single-event effects, and series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)

TL;DR

The paper addresses the challenge of fabricating large, ultra-thin MAPS detectors for the ALICE ITS3 upgrade via wafer-scale stitching. It presents the MOSS prototype as a full-scale demonstration of stitching, interconnects, and large-area pixel readout, including extensive lab and in-beam characterisation, irradiation tests, and SEE studies. Key results show a robust functional yield (≈98% when excluding powering and readout-specific issues), near-target detection efficiency and fake-hit rates, and spatial resolution meeting ITS3 aspirations for an 18 µm pitch. The findings establish the feasibility of stitched wafer-scale MAPS for ITS3, while guiding design optimisations for power distribution, readout architecture, and SEE mitigation in the final sensor implementation, with significant implications for truly cylindrical, low-mass vertex detectors in high-energy physics.

Abstract

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 25.9 cm, thinned to 50 m. The chip architecture, in-pixel front-end, laboratory and in-beam characterisation, susceptibility to single-event effects, and series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

Paper Structure

This paper contains 27 sections, 35 figures.

Table of Contents

  1. Introduction
  2. MOSS sensor
  3. In-pixel front-end
  4. Pixel matrix and biasing
  5. Integration of the pixel sensor within the pixel
  6. Test setup
  7. Testbeam setup
  8. Pixel matrix characterisation
  9. Threshold, noise, and fake-hit rate
  10. Strobe effect on threshold and fake-hit rate
  11. Working point validation of the in-pixel front-end
  12. Time-over-Threshold measurement
  13. Measurements with X-rays
  14. Injection capacitance calibration
  15. Detection efficiency and fake-hit rate
  16. ...and 12 more sections

Figures (35)

  • Figure 1: MOnolithic Stitched Sensor (MOSS) layout. Left End-Cap (LEC), Repeated Sensor Unit (RSU), Right End-Cap (REC), and Stitching Boundaries (SB) are indicated.
  • Figure 2: Processed wafer with 6 numbered MOSS sensors in the centre, and one of the overall 23 babyMOSS sensors labelled near the top of the wafer.
  • Figure 3: MOSS sensor block diagram with one bottom half-unit of a RSU, a LEC, and a REC. Supply, control, and readout lines are schematically indicated. Functional blocks within the half-unit are labelled. The stitched communication backbone spans the full length of the sensor, crossing the stitching boundaries. Region 1 is highlighted, illustrating the contained blocks.
  • Figure 4: Simplified front-end schematic. Control voltages are applied to the gates of the corresponding transistors, while bias currents are provided via current mirrors (indicated as transistors with a current supplied to the gate, e.g. M0). The orange traces illustrate the characteristic voltage signals at key nodes within the front-end circuit.
  • Figure 5: A schematic representation (not to scale) of one region in the bottom half-unit, illustrating the distribution of the tunable analogue bias and the strobe signal to the pixels.
  • ...and 30 more figures