A protocol to reduce worst-case latency in deflection-based on-chip networks

TL;DR

This work tackles worst-case latency in deflection-based, routerless on-chip networks by introducing a header-only deflection protocol that discards the payload during deflection and re-injects it after the header returns to the injection switch. The approach preserves per-packet timing while reducing pre-injection interference, enabling tighter worst-case latency bounds. The authors adapt the existing latency-analysis framework to account for header-only deflections and validate the method with application-specific AV benchmarks and large-scale synthetic studies, showing substantial per-flow improvements (up to ~$93\%$) and notable increases in schedulability under realistic conditions. The protocol achieves these gains without additional buffering, and can be combined with route-change techniques, offering meaningful real-time and energy-efficiency benefits for on-chip interconnects.

Abstract

We present a novel protocol that reduces worst-case packet latency in deflection-based on-chip interconnect networks. It enforces the deflection of the header of a packet but not its payload, resulting in a reduction in overall network traffic and, more importantly, worst-case packet latency due to decreased pre-injection latency.

Figures (3)

• Figure 1: Detail of a routerless network switch architecture as proposed by alazemi_routerless_2018 within a 4x4 network topology with 10 rings generated by the RLrec heuristic.
• Figure 2: Proposed protocol applied to a 4x2 ring.
• Figure 3: Comparative analysis based on schedulability ratio.