Error thresholds of toric codes with transversal logical gates
Yichen Xu, Yiqing Zhou, James P. Sethna, Eun-Ah Kim
TL;DR
This work provides a decoder-agnostic, rigorous bound on how transversal Clifford gates affect the error threshold in toric codes by mapping a two-block tCNOT circuit to classical stat-mech models. For persistent bit-flip errors with perfect syndromes, the problem reduces to a 2D random Ashkin–Teller model, yielding thresholds $p_c^c \approx 0.099$ and $p_c^t \approx 0.080$, both below the memory threshold $p_{th} \approx 0.109$. When syndrome errors are present, the mapping becomes a 3D random 4-body Ising model with a plane defect, conservatively placing the target threshold at $p_c^t \approx 0.028$, still below the memory-case $p^* \approx 0.033$. Overall, the results show that error spreading due to transversal gates modestly lowers decoding thresholds but does not catastrophically degrade fault-tolerance, and establish a general statistical-mechanics framework for analyzing transversal quantum circuits through decoder-agnostic thresholds. The approach offers insights for designing FTQC primitives and suggests potential connections between quantum error thresholds and topological phase transitions.
Abstract
The threshold theorem promises a path to fault-tolerant quantum computation by suppressing logical errors, provided the physical error rate is below a critical threshold. While transversal gates offer an efficient method for implementing logical operations, they risk spreading errors and potentially lowering this threshold compared to a static quantum memory. Available threshold estimates for transversal circuits are empirically obtained and limited to specific, sub-optimal decoders. To establish rigorous bounds on the negative impact of error spreading by the transversal gates, we generalize the statistical mechanical (stat-mech) mapping from quantum memories to logical circuits. We establish a mapping for two toric code blocks that undergo a transversal CNOT (tCNOT) gate. Using this mapping, we quantify the impact of two independent error-spreading mechanisms: the spread of physical bit-flip errors and the spread of syndrome errors. In the former case, the stat-mech model is a 2D random Ashkin-Teller model. We use numerical simulation to show that the tCNOT gate reduces the optimal bit-flip error threshold to $p=0.080$, a $26\%$ decrease from the toric code memory threshold $p=0.109$. The case of syndrome error coexisting with bit-flip errors is mapped to a 3D random 4-body Ising model with a plane defect. There, we obtain a conservative estimate error threshold of $p=0.028$, implying an even more modest reduction due to the spread of the syndrome error compared to the memory threshold $p=0.033$. Our work establishes that an arbitrary transversal Clifford logical circuit can be mapped to a stat-mech model, and a rigorous threshold can be obtained correspondingly.
