Development of 3D Pixel Sensors via an 8-inch CMOS-Compatible Process

TL;DR

This work addresses the need for radiation-hard 3D pixel sensors in next-generation collider experiments by developing devices on a CMOS-compatible 8-inch platform. Using a combination of DRIE (Bosch), in-situ doping, and a back-etching technique, the authors designed, simulated, fabricated, and tested single devices and sensor arrays with trench/column electrodes achieving a high aspect ratio of $70:1$. TCAD simulations guided the design by revealing field concentration near the central electrode, while experimental measurements demonstrated leakage currents below $10$ pA at 20 V and capacitances below $3$ pF, indicating excellent performance in high-radiation environments. The demonstrated yield and uniformity, along with the CMOS-compatible process, lay a solid foundation for large-scale production and integration with readout ASICs for HL-LHC/FCC applications.

Abstract

In the construction of High-Luminosity Large Hadron Collider (HL-LHC) and Future Circular Collider (FCC) experiments, 3D pixel sensors have become indispensable components due to their superior radiation hardness, fast response, and low power consumption. However, there are still significant challenges in the process of 3D sensors manufacturing. In this work, single devices and arrays of 3D sensors based on 30 $μ$m epitaxial silicon wafer have been designed, simulated, fabricated, and tested. This process was developed on the 8-inch CMOS process platform of the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). The key processes include Deep Reactive Ion Etching (DRIE) with the Bosch process, in-situ doping, and an innovative back-etching. After testing the 3D pixel sensors, we have summarized the leakage current and capacitance of devices with different sizes with respect to bias voltages. We also found that the fabricated devices were almost all successfully produced, which laid a strong foundation for subsequent large-scale mass production.

Figures (9)

• Figure 1: Schematic of the single device structure.
• Figure 2: (a) The potential distribution with a reverse bias voltage of 40 V. (b) The electric field distribution with a reverse bias voltage of 40 V. (c) The electric field distribution with a reverse bias voltage of 60 V. (d) The one-dimensional transverse electric field distribution at the depths of 25 $\mu$m and 15 $\mu$m for the device under different bias voltages.
• Figure 3: Layouts of the (a) square single device, (b) circular single device, (c) array with a pixel size of 80 $\mu$m $\times$ 80 $\mu$m, and (d) single device in the array with a pixel size of 80 $\mu$m $\times$ 80 $\mu$m of 3D pixel sensors.
• Figure 4: Fabrication processes of the single device of 3D pixel sensors.
• Figure 5: The images of the trenches of 3D pixel sensors by using ultra high resolution scanning electron microscope (S-5500). (a) Etching depth corresponding to different trench/column width under the same etching time. (b) Surface image of the back-etching process of polysilicon on the 3D electrode. (c) The cross-sectional view of the 3D trench after the back-etching process of polysilicon on the 3D electrode. (d) The surface image of the central electrode vias etching.