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Causal-Guided Dimension Reduction for Efficient Pareto Optimization

Dinithi Jayasuriya, Divake Kumar, Sureshkumar Senthilkumar, Devashri Naik, Nastaran Darabi, Amit Ranjan Trivedi

TL;DR

CaDRO tackles high-dimensional analog circuit optimization by learning a causal map that identifies true design drivers and fixes low-impact parameters. It integrates causal discovery with NSGA-II in three phases—causal discovery, dimensionality reduction, and focused optimization—achieving up to $10\times$ faster convergence while preserving or improving Pareto fronts. The approach yields interpretable causal strengths that reveal which parameters govern performance, with experiments across amplifiers, regulators, and RF blocks showing substantial speedups and improved hypervolume. This framework enables scalable design automation with preserved solution quality and actionable design insights.

Abstract

Multi-objective optimization of analog circuits is hindered by high-dimensional parameter spaces, strong feedback couplings, and expensive transistor-level simulations. Evolutionary algorithms such as Non-dominated Sorting Genetic Algorithm II (NSGA-II) are widely used but treat all parameters equally, thereby wasting effort on variables with little impact on performance, which limits their scalability. We introduce CaDRO, a causal-guided dimensionality reduction framework that embeds causal discovery into the optimization pipeline. CaDRO builds a quantitative causal map through a hybrid observational-interventional process, ranking parameters by their causal effect on the objectives. Low-impact parameters are fixed to values from high-quality solutions, while critical drivers remain active in the search. The reduced design space enables focused evolutionary optimization without modifying the underlying algorithm. Across amplifiers, regulators, and RF circuits, CaDRO converges up to 10$\times$ faster than NSGA-II while preserving or improving Pareto quality. For instance, on the Folded-Cascode Amplifier, hypervolume improves from 0.56 to 0.94, and on the LDO regulator from 0.65 to 0.81, with large gains in non-dominated solutions.

Causal-Guided Dimension Reduction for Efficient Pareto Optimization

TL;DR

CaDRO tackles high-dimensional analog circuit optimization by learning a causal map that identifies true design drivers and fixes low-impact parameters. It integrates causal discovery with NSGA-II in three phases—causal discovery, dimensionality reduction, and focused optimization—achieving up to faster convergence while preserving or improving Pareto fronts. The approach yields interpretable causal strengths that reveal which parameters govern performance, with experiments across amplifiers, regulators, and RF blocks showing substantial speedups and improved hypervolume. This framework enables scalable design automation with preserved solution quality and actionable design insights.

Abstract

Multi-objective optimization of analog circuits is hindered by high-dimensional parameter spaces, strong feedback couplings, and expensive transistor-level simulations. Evolutionary algorithms such as Non-dominated Sorting Genetic Algorithm II (NSGA-II) are widely used but treat all parameters equally, thereby wasting effort on variables with little impact on performance, which limits their scalability. We introduce CaDRO, a causal-guided dimensionality reduction framework that embeds causal discovery into the optimization pipeline. CaDRO builds a quantitative causal map through a hybrid observational-interventional process, ranking parameters by their causal effect on the objectives. Low-impact parameters are fixed to values from high-quality solutions, while critical drivers remain active in the search. The reduced design space enables focused evolutionary optimization without modifying the underlying algorithm. Across amplifiers, regulators, and RF circuits, CaDRO converges up to 10 faster than NSGA-II while preserving or improving Pareto quality. For instance, on the Folded-Cascode Amplifier, hypervolume improves from 0.56 to 0.94, and on the LDO regulator from 0.65 to 0.81, with large gains in non-dominated solutions.

Paper Structure

This paper contains 14 sections, 1 equation, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Causal Discovery
  4. Non-Dominated Sorting Genetic Algorithm II (NSGA-II)
  5. CaDRO: Causal-Guided Dimensionality Reduction for Multi-Objective Optimization
  6. Phase 1: Causal Discovery and Strength Analysis
  7. Phase 2: Causal-Based Dimensionality Reduction
  8. Phase 3: Focused Multi-Objective Optimization
  9. Results and Evaluation
  10. Benchmark Circuits and Design Objectives
  11. Discovered Causal Strengths
  12. Impact of Causal Pruning on Pareto Trade-Offs
  13. Quantitative Benchmarking
  14. Conclusion

Figures (5)

  • Figure 1: CaDRO framework: Phase 1 learns the causal graph of the circuit under test (CUT). Phase 2 prunes weak parameters via causal strength estimation. Phase 3 performs Pareto optimization on the reduced space, achieving near full-space performance with lower complexity.
  • Figure 2: Schematics of benchmark circuits used to evaluate CaDRO: (a) Active-Load Differential Amplifier, (b) Folded-Cascode Amplifier, (c) Two-Stage Voltage Amplifier, (d) Two-Stage Operational Transconductance Amplifier, (e) Voltage-Controlled Oscillator, and (f) Low-Dropout Regulator.
  • Figure 3: Causal strength of input parameters across benchmark circuits: Each subplot shows normalized causal strengths from CaDRO's observational–interventional analysis. (a) ALDA, (b) FCA, (c) TSOTA, (d) VCO, (e) TSVA, and (f) LDO. Markers denote circuit objectives (e.g., Gain, UGBW, Power, PSRR). The profiles highlight dominant drivers and low-impact parameters that can be pruned safely.
  • Figure 4: Amplifier benchmarks under CaDRO vs. full-space NSGA-II: (a–c) Pareto fronts for the Two-Stage OTA (TSOTA), Folded-Cascode Amplifier (FCA), and Active-Load Differential Amplifier (ALDA), comparing reduced-space CaDRO (red) against full-space NSGA-II (blue). CaDRO consistently produces outward-shifted and denser Pareto fronts. (d–f) Best and mean values of Gain and Unity-Gain Bandwidth from the corresponding fronts. In TSOTA (d), CaDRO sacrifices some gain (–24%) but slightly improves UGBW (+2%). In FCA (e), CaDRO achieves a large gain improvement (+64%) together with higher UGBW (+3%). In ALDA (f), gain decreases (–26%) while UGBW is preserved (+1%). These plots show that causal pruning redistributes search effort: in circuits where causal drivers strongly govern both objectives (FCA), fronts expand dramatically, while in others (TSOTA, ALDA), fronts densify and trade-offs shift.
  • Figure 5: Oscillator and Regulator benchmarks under CaDRO vs. full-space NSGA-II: (a–c) Voltage-Controlled Oscillator (VCO) and (d–f) Two-Stage Voltage Amplifier (TSVA). Reduced-space CaDRO (red) achieves fronts nearly identical to full-space NSGA-II (blue) but with far fewer evaluations. In the VCO, CaDRO maintains trade-offs across oscillation frequency, power, phase noise, and tuning range, while avoiding wasted exploration of weakly causal parameters. In the TSVA, fronts in gain, bandwidth, and power consumption closely track the baseline yet are reached with an order-of-magnitude fewer simulations.