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THEAS: Efficient Power Management in Multi-Core CPUs via Cache-Aware Resource Scheduling

Said Muhammad, Lahlou Laaziz, Nadjia Kara, Phat Tan Nguyen, Timothy Murphy

TL;DR

THEAS introduces cache-aware resource scheduling for multicore ARM CPUs to address power efficiency under heterogeneous, non-pinning workloads. By leveraging PMCs (notably IPC and cache misses) and an empirical power model, THEAS dynamically adjusts per-core resource levels and assigns tasks to appropriate cores within Gem5, and it is benchmarked against standard schedulers (CFS, EAS, HeteroSched, Utility-Based) for performance-power trade-offs. The approach is validated with both Gem5 simulations and real Raspberry Pi 4 hardware, showing measurable power reductions (up to ~$4.6\%$–$4.8\%$) without degrading performance and maintaining reasonable modeling accuracy ($\approx5.6\%$). This work demonstrates a practical framework for energy-aware scheduling in heterogeneous, cache-sensitive multicore environments and points to future extensions involving per-core DVFS and uncore integration for broader applicability.

Abstract

The dynamic adaptation of resource levels enables the system to enhance energy efficiency while maintaining the necessary computational resources, particularly in scenarios where workloads fluctuate significantly over time. The proposed approach can play a crucial role in heterogeneous systems where workload characteristics are not uniformly distributed, such as non-pinning tasks. The deployed THEAS algorithm in this research work ensures a balance between performance and power consumption, making it suitable for a wide range of real-time applications. A comparative analysis of the proposed THEAS algorithm with well-known scheduling techniques such as Completely Fair Scheduler (CFS), Energy-Aware Scheduling (EAS), Heterogeneous Scheduling (HeteroSched), and Utility-Based Scheduling is presented in Table III. Each scheme is compared based on adaptability, core selection criteria, performance scaling, cache awareness, overhead, and real-time suitability.

THEAS: Efficient Power Management in Multi-Core CPUs via Cache-Aware Resource Scheduling

TL;DR

THEAS introduces cache-aware resource scheduling for multicore ARM CPUs to address power efficiency under heterogeneous, non-pinning workloads. By leveraging PMCs (notably IPC and cache misses) and an empirical power model, THEAS dynamically adjusts per-core resource levels and assigns tasks to appropriate cores within Gem5, and it is benchmarked against standard schedulers (CFS, EAS, HeteroSched, Utility-Based) for performance-power trade-offs. The approach is validated with both Gem5 simulations and real Raspberry Pi 4 hardware, showing measurable power reductions (up to ~–) without degrading performance and maintaining reasonable modeling accuracy (). This work demonstrates a practical framework for energy-aware scheduling in heterogeneous, cache-sensitive multicore environments and points to future extensions involving per-core DVFS and uncore integration for broader applicability.

Abstract

The dynamic adaptation of resource levels enables the system to enhance energy efficiency while maintaining the necessary computational resources, particularly in scenarios where workloads fluctuate significantly over time. The proposed approach can play a crucial role in heterogeneous systems where workload characteristics are not uniformly distributed, such as non-pinning tasks. The deployed THEAS algorithm in this research work ensures a balance between performance and power consumption, making it suitable for a wide range of real-time applications. A comparative analysis of the proposed THEAS algorithm with well-known scheduling techniques such as Completely Fair Scheduler (CFS), Energy-Aware Scheduling (EAS), Heterogeneous Scheduling (HeteroSched), and Utility-Based Scheduling is presented in Table III. Each scheme is compared based on adaptability, core selection criteria, performance scaling, cache awareness, overhead, and real-time suitability.

Paper Structure

This paper contains 12 sections, 5 equations, 16 figures, 4 tables, 1 algorithm.

Table of Contents

  1. INTRODUCTION
  2. Related Work
  3. Proposed Approach Implementation Framework
  4. Gem5 setup and its Evaluation
  5. Gem5 CPU model
  6. Accuracy evaluation
  7. Core-based resource adaption in Gem5
  8. THEAS algorithm
  9. Experimental Setup, Results and Discussion
  10. Empirical Power Model Evaluation Using Gem5
  11. Workload validation on Real Hardware
  12. Conclusion

Figures (16)

  • Figure 1: Retrieval and deployment of PMC events along with THEAS and core-based resource level on Gem5.
  • Figure 2: Gem5 with real hardware accuracy evaluation process.
  • Figure 3: Cores adaptation for dynamically scheduled threads in a non-pinning-based workload.
  • Figure 8: Hardware of ARM cortex-A72 (Raspberry Pi4).
  • Figure : (a) CPU 0 Dynamic Power
  • ...and 11 more figures