Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge
Sebastian Magierowski, Zhongpan Wu, Abel Beyene, Karim Hammad
TL;DR
The paper addresses the challenge of real-time, on-device genomics processing at the edge, driven by high data rates from miniature DNA sequencers. It proposes a hardware/software co-design SoC built around two Linux-capable RISC-V cores and two bioinformatics accelerators (MAT and ED) to run basecalling and lightweight alignment in energy-constrained mobile contexts. The authors implement a CNN-based basecaller (~450K parameters) on the MAT engine and report substantial speedups and energy efficiency gains, along with preliminary end-to-end alignment and variant-calling considerations and FPGA benchmarking results. This work demonstrates the feasibility of mobile genomics at the edge and outlines a path toward pathogen detection and real-time genome analysis in edge devices, with room for improvements in throughput and DP-based pipelines.
Abstract
Miniature DNA sequencing hardware has begun to succeed in mobile contexts, driving demand for efficient machine learning at the edge. This domain leverages deep learning techniques familiar from speech and time-series analysis for both low-level signal processing and high-level genomic interpretation. Unlike audio, however, nanopore sequencing presents raw data rates over 100X higher, requiring more aggressive compute and memory handling. In this paper, we present a CMOS system-on-chip (SoC) designed for mobile genetic analysis. Our approach combines a multi-core RISC-V processor with tightly coupled accelerators for deep learning and bioinformatics. A hardware/software co-design strategy enables energy-efficient operation across a heterogeneous compute fabric, targeting real-time, on-device genome analysis. This work exemplifies the integration of deep learning, edge computing, and domain-specific hardware to advance next-generation mobile genomics.