Lithographic integration of TES microcalorimeters with SQUID multiplexer circuits for large format spectrometers

TL;DR

This work demonstrates the first lithographic integration of soft X-ray TES microcalorimeters with microwave μMUX readout on a single wafer (TES-SoC), using lithographically defined interconnects to replace wirebonds and dramatically increase focal-plane fill factor. The authors develop a fabrication flow on bulk silicon to validate TES, μMUX, and interconnect integration, and outline a path to SOI-based membranes to enable high pixel density (≈10,000 TES pixels) with 1 MHz μMUX bandwidth for next-generation X-ray spectrometers. Experimental results show a functional μMUX with high yield, measurable flux-induced resonator shifts, and TES Tc around 141 mK on the integrated chip, though thermal isolation challenges in the bulk-Si demonstration highlight the need for membrane-based suspension. Box-mode resonances in the larger die are identified as a source of Q_i degradation, guiding future design improvements such as grounding structures and SOI-based TES membranes. Overall, the TES-SoC approach proves viable for large-format, high-resolution X-ray spectroscopy and can significantly reduce packaging complexity while enabling scalable pixel densities.

Abstract

Arrays of hundreds or thousands of low temperature detectors have been deployed for many experiments, both bolometers for long wavelength applications and calorimeters for shorter wavelength applications. One challenge that is common to many of these arrays is the efficient use of focal plane area to achieve a large fill fraction of absorbers coupled to detectors. We are developing an integrated fabrication of soft X-ray transition edge sensors (TES) and microwave SQUID multiplexers ($μ$MUX) with the goal of maximizing the fill fraction of the focal plane area on a scale of many thousand pixel detectors. We will utilize lithographically defined high density interconnects to circumvent limitations in existing solutions that use wirebonds or flip-chip bonds. Here we report the first demonstration of combining TES and $μ$MUX processes into a single TES-System-on-a-Chip (TES-SoC) fabrication on a silicon wafer. The $μ$MUX SQUIDs and TES electrothermal feedback circuits are microfabricated first and protected with passivating SiO$_2$, then the TES devices and TES-to-SQUID interconnects are fabricated, and finally the protective layer is removed before the fabrication of the microwave resonators. We show that the microwave SQUIDs are functional and have reasonable yield, and that we are able to read out the transition temperature of the connected TESs using those SQUIDs.

Figures (7)

• Figure 1: Layer schematic (not to scale) showing the microfabrication steps for TES-SoC on bulk Si. First, Nb-Al/Al$_x$O$_y$-Nb SIS trilayer is grown as L1. L2-L4 are etch steps for Nb counter-electrode (CE), aluminum (Al), and Nb base-electrode (BE) layers of SIS trilayers, respectively. Pd$_{0.53}$Au$_{0.47}$ shunt resistors are deposited as L5 using liftoff process. L6 and L7 include deposition of passivating PECVD SiO$_2$ (I1) and etching into I1 to open vias. Subsequent L8 layer is the deposition and etching of Nb (W1) that forms interconnects and termination wiring circuits using I1 vias. For layers L9 and L10, first I1 is removed in areas where microwave resonators, TES detectors, and TES-to-SQUID interconnects will be fabricated, then another layer of passivating SiO$_2$ (I2) is deposited to protect $\mu$MUX electronics. In L11, I2 is removed from areas where TES detectors and TES-to-SQUID interconnects will be fabricated, then a thin layer of molybdenum (Mo) is sputter-deposited, patterned, and etched using wet chemical bath. L12 is e-beam liftoff deposition of gold (Au) completing our MoAu bilayer TES detectors. L13 and L14 include RIE etching of vias into I2 and deposition of liftoff Nb to form TES-to-SQUID wiring interconnects. As final steps (L15 and L16), I2 and BE niobium are etched to form microwave resonators. The wafer is then diced into individual dies (step not shown in this schematic)
• Figure 2: Optical micrograph of a TES-SoC die showing MoAu bilayer based TES detectors, IF electronics, and $\mu$MUX readout integrated onto a single monolithic wafer platform. The chip dimension are 10 mm $\times$ 20 mm. TES detectors are fabricated directly on bulk silicon and are not suspended. (a), (b), (c), (d), and (e) are higher magnification optical micrographs of the TES detectors, TES-to-SQUID liftoff niobium interconnects, Nyquist inductors, shunt resistors, and the $\mu$MUX resonators, respectively.
• Figure 3: Data showing shifts in the resonant frequencies of the 32 resonators on TES-SoC, as a function of applied magnetic flux. An x-axis offset is applied to match the phase between all channels. The average value of M$_{in}$$\sim$ 9.2 pH is calculated by fitting the frequency shifts to theoretical models.
• Figure 4: Histograms showing (a) the frequency spacings between resonators, (b) the bandwidth of resonators for the $\mu$MUX channels on the TES-SoC.
• Figure 5: Histogram showing $\lambda$ spread of all the $\mu$MUX channels on the TES-SoC.