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In-pixel integration of signal processing and AI/ML based data filtering for particle tracking detectors

Benjamin Parpillon, Anthony Badea, Danush Shekar, Christian Gingu, Giuseppe Di Guglielmo, Tom Deline, Adam Quinn, Michele Ronchi, Benjamin Weiss, Jennet Dickinson, Jieun Yoo, Corrinne Mills, Daniel Abadjiev, Aidan Nicholas, Eliza Howard, Carissa Kumar, Eric You, Mira Littmann, Karri DiPetrillo, Arghya Ranjan Das, Mia Liu, David Jiang, Mark S. Neubauer, Morris Swartz, Petar Maksimovic, Alice Bean, Ricardo Silvestre, Jannicke Pearkes, Keith Ulmer, Nick Manganelli, Chinar Syal, Doug Berry, Nhan Tran, Lindsey Gray, Farah Fahim

TL;DR

This paper reports the first physical demonstration of in-pixel signal processing with an integrated AI-based data filter for particle tracking detectors, realized on a 28 nm TSMC ROIC (SmartPix v1) containing two 32×8 pixel arrays. Each pixel combines an analog front-end with a digital back-end NN, projecting 256 pixels to 16 buses of 6-bit data that feed a two-layer NN for momentum classification, all implemented with zero-latency combinatorial logic and high-level synthesis. The authors characterize the analog front-end (ENC ~58 e^- and threshold dispersion ~90 e^-, with simulated CvG ≈ 58.5 μV/e^-) and demonstrate on-chip NN performance that closely matches offline models, achieving a 99.86% RTL–chip agreement over 10k test vectors. These results establish a path toward fully on-detector edge AI, enabling substantial data reduction and improved discovery potential in high-rate, radiation-intense environments such as HL-LHC, while outlining concrete design refinements for next iterations.

Abstract

We present the first physical realization of in-pixel signal processing with integrated AI-based data filtering for particle tracking detectors. Building on prior work that demonstrated a physics-motivated edge-AI algorithm suitable for ASIC implementation, this work marks a significant milestone toward intelligent silicon trackers. Our prototype readout chip performs real-time data reduction at the sensor level while meeting stringent requirements on power, area, and latency. The chip is taped-out in 28nm TSMC CMOS bulk process, which has been shown to have sufficient radiation hardness for particle experiments. This development represents a key step toward enabling fully on-detector edge AI, with broad implications for data throughput and discovery potential in high-rate, high-radiation environments such as the High-Luminosity LHC.

In-pixel integration of signal processing and AI/ML based data filtering for particle tracking detectors

TL;DR

This paper reports the first physical demonstration of in-pixel signal processing with an integrated AI-based data filter for particle tracking detectors, realized on a 28 nm TSMC ROIC (SmartPix v1) containing two 32×8 pixel arrays. Each pixel combines an analog front-end with a digital back-end NN, projecting 256 pixels to 16 buses of 6-bit data that feed a two-layer NN for momentum classification, all implemented with zero-latency combinatorial logic and high-level synthesis. The authors characterize the analog front-end (ENC ~58 e^- and threshold dispersion ~90 e^-, with simulated CvG ≈ 58.5 μV/e^-) and demonstrate on-chip NN performance that closely matches offline models, achieving a 99.86% RTL–chip agreement over 10k test vectors. These results establish a path toward fully on-detector edge AI, enabling substantial data reduction and improved discovery potential in high-rate, radiation-intense environments such as HL-LHC, while outlining concrete design refinements for next iterations.

Abstract

We present the first physical realization of in-pixel signal processing with integrated AI-based data filtering for particle tracking detectors. Building on prior work that demonstrated a physics-motivated edge-AI algorithm suitable for ASIC implementation, this work marks a significant milestone toward intelligent silicon trackers. Our prototype readout chip performs real-time data reduction at the sensor level while meeting stringent requirements on power, area, and latency. The chip is taped-out in 28nm TSMC CMOS bulk process, which has been shown to have sufficient radiation hardness for particle experiments. This development represents a key step toward enabling fully on-detector edge AI, with broad implications for data throughput and discovery potential in high-rate, high-radiation environments such as the High-Luminosity LHC.

Paper Structure

This paper contains 21 sections, 8 equations, 16 figures, 2 tables.

Table of Contents

  1. Introduction
  2. SmartPix ASIC v1 overview
  3. Test setup
  4. Data acquisition system
  5. Timing and calibrations
  6. Charge injection and S-curve measurement
  7. Clock and phase alignment
  8. Firmware timing window
  9. Analog front-end characterization
  10. Analog Power
  11. Conversion Gain
  12. Linearity
  13. Threshold Dispersion and Equivalent Noise Charge
  14. Conceptual Model
  15. Experimental Extraction from S-Curves
  16. ...and 6 more sections

Figures (16)

  • Figure 1: Architecture of a single analog front-end pixel. In the prototype ROIC there are 256 such pixels arranged in a 8x32 grid. The output of each pixel is input to the digital logic surrounding the analog islands. We refer to the threshold on bits 0, 1, and 2 as V$_{th0}$, V$_{th1}$, and V$_{th2}$, respectively.
  • Figure 2: ASIC-level layout illustrating the two superpixel variants (left) and a close-up view of a $2\times2$ pixel block (right). The central analog island shares a common deep-nwell substrate isolated from the surrounding digital region, which contains the configuration logic and machine-learning circuitry.
  • Figure 3: Architecture 2-layer fully connected NN that performs momentum filtering based on the cluster profile created by incident particles.
  • Figure 4: Test stand for the SmartPixel ASIC. The device under test (DUT), a custom PCB with the bonded ROIC, connects via a SEARAY connector to the CaR Board, which interfaces with a Xilinx ZCU102 SoC FPGA running the Peary server and connected to a workstation executing the python test routines (not shown). External power supplies bias the DUT and CaR Board. An external pulse generator supplies high quality pulses.
  • Figure 5: (a) Typical S-curves for the three bits of one pixel (0–5000e^- in 20e^- steps; 1365 samples/step). (b) ENC vs pulse fall time with an upward trend in apparent ENC.
  • ...and 11 more figures