A Hardware-Efficient Mølmer-Sørensen Gate for Superconducting Quantum Computers

TL;DR

The paper addresses whether a non-native Mølmer-Sørensen entangling gate can be effectively realized on superconducting hardware, proposing hardware-aware compilation to native gates and validating with direct state measurements and quantum process tomography on IBM devices, with a comparison to CX. It reports hardware process fidelity $F_p^{hw}=0.9247$, simulator fidelity $F_p^{sim}=0.9686$, Bell-state preparation probability $P_{succ}=0.942$ for input |00>, and CX fidelity $F_p^{CX}=0.9302$, demonstrating parity between MS and CX performance. These results expand the practical gate set for fixed-architecture quantum processors and provide a cross-platform benchmark for gate evaluation, highlighting the role of hardware-aware compilation in NISQ-era computing. Overall, the work shows that carefully compiled non-native gates can approach native-gate performance, enabling more flexible circuit decompositions and algorithm optimizations across platforms.

Abstract

The Mølmer-Sørensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the Mølmer-Sørensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum's superconducting processors. Our implementation achieves a process fidelity of 92.47\% on the real quantum hardware, a performance competitive with the 93.02\% fidelity of the device's native controlled-NOT (CX) gate. Furthermore, for the $|00\rangle$ input state, the gate prepares the target Bell state with $94.2\%$ success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.

Figures (4)

• Figure 1: Hardware-efficient circuit compilation of the Mølmer-Sørensen gate. Decomposition of the Mølmer-Sørensen gate unitary into the native gate set (R$_Z$, $\sqrt{X}$, CNOT) of a superconducting quantum processor. This optimized implementation, requiring only one CNOT gate, enables high-fidelity execution on fixed-architecture hardware. The circuit respects the physical connectivity constraints of the target device.
• Figure 2: Measurement-based validation of the Mølmer-Sørensen gate on a superconducting quantum processor. Measurement outcomes for the input state $|00\rangle$, comparing results from a noiseless quantum simulator (blue) and hardware execution on ibm_nairobi (red). The ideal simulated output shows the expected Bell state profile, with population confined to the $|00\rangle$ and $|11\rangle$ states. The hardware results demonstrate a 94.2% success probability within the correct subspace, with a 5.8% population leakage into erroneous computational basis states ($|01\rangle$ and $|10\rangle$), quantifying the gate's implementation infidelity. Data from 13,000 shots per execution.
• Figure 3: Quantum process tomography of the Mølmer-Sørensen gate. Reconstructed process matrices (Choi matrices) from (a) Ideal theoretical process matrix ($\mathcal{F}_p^{CZ} = 1.0$). (b) noiseless simulation (process fidelity = 0.969), and (c) hardware execution on ibm_nairobi (process fidelity = 0.925). The high overlap between the experimental and ideal processes confirms the successful implementation of the target unitary on quantum hardware.
• Figure 4: Comprehensive stability analysis of superconducting quantum processor performance across experimental campaigns. (a) T1 coherence time comparison showing 26.2% average variation between implementation and QPT experiments. (b) T2 dephasing time comparison demonstrating 15.5% average stability with Q6 exhibiting superior coherence. (c) Readout error analysis revealing consistent performance below 5% threshold except for Q5. (d) Parameter stability heatmap quantifying percentage variations across all qubits and metrics. (e) Quality correlation scatter plot showing strong consistency between experimental campaigns ($r = 0.894$). (f) Statistical summary highlighting key performance metrics and stability observations. The analysis demonstrates robust device performance suitable for high-fidelity quantum gate implementations, with quality rankings remaining stable despite absolute parameter variations.